公开(公告)号：KR1020160069430A

公开(公告)日：2016-06-16

申请号：KR1020140175375

申请日：2014-12-08

Applicant: 삼성전자주식회사

Inventor： 현기호 ,  류제민 ,  설호석 ,  손교민

IPC: G11C11/406 ,  G11C11/402 ,  G11C11/4091 ,  G11C7/10

CPC classification number: G11C11/4087 ,  G11C11/40611 ,  G11C11/40622 ,  G11C11/4093 ,  G11C2211/4061 ,  G11C11/406 ,  G11C7/1021 ,  G11C7/1063 ,  G11C11/402 ,  G11C11/4091 ,  G11C2211/4065

Abstract: 본발명은셀 특성플래그를이용하여리프레쉬동작을제어하는메모리장치에대하여개시된다. 메모리장치는리프레쉬주기보다짧은데이터보유시간을가지는적어도하나의메모리셀을포함하는위크셀 로우를나타내는위크셀 플래그또는리프레쉬주기보다긴 데이터보유시간을가지는메모리셀들만을포함하는스트롱셀 로우를나타내는스트롱셀 플래그를리프레쉬로우어드레스에대응하여저장하는플래그저장부를포함할수 있다. 메모리장치는위크셀 로우를리프레쉬주기보다짧은주기로리프레쉬하고, 스트롱셀 로우를리프레쉬주기보다긴 주기로리프레쉬하고, 메모리셀 로우들중 위크셀 로우및 스트롱셀 로우를제외한노멀셀 로우들을리프레쉬주기로리프레쉬할수 있다.

Abstract translation: 本发明公开了一种通过使用单元特性标志来控制刷新操作的存储装置。 存储装置可以包括标志存储单元，其存储表示弱单元行的弱单元标志，所述弱单元行包括具有短于刷新周期的短数据保持时间的至少一个存储单元或表示强单元行的强单元标志，包括 仅具有响应于刷新行地址而比刷新周期长的数据保留时间的存储器单元。 存储器件在比刷新周期短的周期内刷新弱单元行，刷新长于刷新周期的周期内的强单元行，并刷新存储单元行的正常单元行，除了弱 单元格行和强单元格行，在刷新期间。

公开(公告)号：KR1020130115066A

公开(公告)日：2013-10-21

申请号：KR1020120095591

申请日：2012-08-30

Applicant: 삼성전자주식회사

Inventor： 손교민

IPC: G11C11/408 ,  G11C11/406

CPC classification number: G11C11/408 ,  G11C11/406 ,  G11C29/808

Abstract: PURPOSE: A concentrated address caring method and a memory system with a concentrated address caring function are provided to guarantee the data retention reliability of memory cells adjacent to access-concentrated memory cells by reducing stress to be applied to the memory cells. CONSTITUTION: A semiconductor memory device (300) of a memory system includes a semiconductor memory cell array and a concentrated address processing part (301). A demultiplexer demultiplexes a concentrated row address according to a control signal. An adjacent row address extractor extracts adjacent row addresses from the concentrated row address outputted from the demultiplexer. A multiplexer selects an adjacent row address from the extracted adjacent row addresses according to a selection control signal and outputs the selected adjacent row address.

Abstract translation: 目的：提供集中地址关注方法和具有集中地址关系功能的存储系统，以通过减少应用于存储单元的应力来保证与访问集中存储单元相邻的存储单元的数据保留可靠性。 构成：存储器系统的半导体存储器件（300）包括半导体存储单元阵列和集中地址处理部分（301）。 解复用器根据控制信号解复用集中行地址。 相邻行地址提取器从从解复用器输出的集中行地址中提取相邻的行地址。 复用器根据选择控制信号从所提取的相邻行地址中选择相邻的行地址，并输出所选择的相邻行地址。

公开(公告)号：KR1020130098681A

公开(公告)日：2013-09-05

申请号：KR1020120020397

申请日：2012-02-28

Applicant: 삼성전자주식회사

Inventor： 손교민

IPC: G11C7/10 ,  G11C7/22

CPC classification number: G11C7/1009 ,  G11C5/02 ,  G11C5/06 ,  G11C7/1006 ,  G11C7/1045 ,  G11C7/1096 ,  G11C7/12 ,  G11C7/22 ,  G11C11/1675 ,  G11C11/4085 ,  G11C11/4096 ,  G11C11/4097 ,  G11C2211/5647

Abstract: PURPOSE: A semiconductor memory device reduces power consumed in the semiconductor memory device by arranging a circuit performing a data inversion function around a memory cell. CONSTITUTION: A cell/core region (CELL/CORE) includes multiple memory banks (BANK) and multiple memory cell arrays (101). A data terminal to which an input data signal is inputted is placed on a peripheral region (PERI). An inversion circuit outputs the input data signal which is inverted or non-inverted in response to an inversion control signal indicating the inversion state of the input data signal. The multiple memory banks have one inversion circuit, respectively.

Abstract translation: 目的：半导体存储器件通过布置在存储单元周围执行数据反转功能的电路来减少半导体存储器件中的功耗。 构成：单元/核心区域（CELL / CORE）包括多个存储体（BANK）和多个存储单元阵列（101）。 输入数据信号的数据端子被放置在周边区域（PERI）上。 反相电路响应于指示输入数据信号的反转状态的反转控制信号输出反相或非反相的输入数据信号。 多个存储体分别具有一个反相电路。

公开(公告)号：KR1020100109773A

公开(公告)日：2010-10-11

申请号：KR1020090028200

申请日：2009-04-01

Applicant: 삼성전자주식회사

Inventor： 손교민

IPC: G11C7/10 ,  H03K19/0175

CPC classification number: H03K19/00361 ,  H03K19/018585

Abstract: PURPOSE: A semiconductor device is provided to secure signal integrity regardless of output driving performance by including a constant slew rate. CONSTITUTION: A mode register(50) outputs a driving performance first control signal. A pull-up slow rate controller(100) successively outputs output data and first to third delay output data. A pull-up free driver(200) outputs a plurality of pull-up control signals. A pull-down free driver(500) outputs a plurality of pull-down control signals. A pull-down slew rate controller(400) successively generates first to third delay pull-down data.

Abstract translation: 目的：提供一种半导体器件，通过包括恒定的转换速率，无论输出驱动性能如何，都能确保信号完整性。 构成：模式寄存器（50）输出驾驶性能第一控制信号。 上拉慢速率控制器（100）依次输出输出数据和第一至第三延迟输出数据。 上拉自由驱动器（200）输出多个上拉控制信号。 下拉自由驱动器（500）输出多个下拉控制信号。 下拉压摆率控制器（400）连续产生第一至第三延迟下拉数据。

公开(公告)号：KR1020100040217A

公开(公告)日：2010-04-19

申请号：KR1020080099344

申请日：2008-10-09

Applicant: 삼성전자주식회사

Inventor： 손영훈 ,  박광일 ,  손교민

IPC: G11C7/04 ,  G11C7/10

CPC classification number: G11C7/1051 ,  G01K7/01 ,  G11C7/04 ,  G11C2207/2254

Abstract: PURPOSE: A semiconductor IC and a driving method thereof are provided to compensate the characteristic change of an output voltage by using an output code of a temperature sensor. CONSTITUTION: A temperature sensor(110) outputs a temperature code by detecting the temperature of the integrated circuit. A code converter(120) receives a predetermined ZQ calibration code and the temperature code. The code converter outputs an enable code by computing the ZQ calibration code and the temperature code. An output driver(130) receives an enable code. The output driver controls the driver strength according to the enable code value.

Abstract translation: 目的：提供半导体IC及其驱动方法，以通过使用温度传感器的输出代码补偿输出电压的特性变化。 构成：温度传感器（110）通过检测集成电路的温度来输出温度代码。 代码转换器（120）接收预定的ZQ校准代码和温度代码。 代码转换器通过计算ZQ校准代码和温度代码来输出使能代码。 输出驱动器（130）接收使能码。 输出驱动器根据使能码值控制驱动器强度。

公开(公告)号：KR1020040089894A

公开(公告)日：2004-10-22

申请号：KR1020030023732

申请日：2003-04-15

Applicant: 삼성전자주식회사

Inventor： 손교민 ,  서영호

IPC: G11C11/40

CPC classification number: G11C8/16 ,  G11C7/22

Abstract: PURPOSE: A method for controlling the operation of an integrated circuit capable of performing a read operation and a write operation simultaneously is provided to smoothly write or read the data without affecting to the period of the clock signal. CONSTITUTION: A method for controlling the operation of an integrated circuit capable of performing a read operation and a write operation simultaneously includes the steps of: (a) receiving(710) a write address, a read address and a write data; (b) determining(720) where the read and write operation of the data are performed at any one of the memory blocks and the data memory blocks in response to the write address and the read address; (c) performing(730) the read or write operation in the data memory block in response to the result of the step(b); and (d) performing(740) the read or write operation in the memory block in response to the result of the step(b).

Abstract translation: 目的：提供一种能够同时执行读取操作和写入操作的集成电路的操作控制方法，以平滑地写入或读取数据，而不影响时钟信号的周期。 构成：一种用于控制能够同时执行读取操作和写入操作的集成电路的操作的方法，包括以下步骤：（a）接收（710）写入地址，读取地址和写入数据; （b）确定（720）响应于写入地址和读取地址在数据存储器块和数据存储器块中的任何一个执行数据的读取和写入操作的步骤（720） （c）响应于步骤（b）的结果，在数据存储器块中执行（730）读或写操作; 以及（d）响应于步骤（b）的结果，在存储块中执行（740）读或写操作。

公开(公告)号：KR1020040036477A

公开(公告)日：2004-04-30

申请号：KR1020020065682

申请日：2002-10-26

Applicant: 삼성전자주식회사

Inventor： 손교민 ,  서영호

IPC: G11C7/00

CPC classification number: G06F12/0893 ,  G06F2212/3042 ,  G11C7/22 ,  G11C11/4076 ,  G11C2207/2245 ,  G11C2207/2281 ,  G11C2207/229

Abstract: PURPOSE: An integrated circuit capable of performing a data read operation and a data write operation at the same time and its method are provided to increase an operating frequency of a clock signal. CONSTITUTION: According to the integrated circuit(200) where an input port and an output port are separated and a write address(WADD) and a read address(RADD) are inputted during one period of a clock signal, memory blocks(MB1,MB2,MB3,MB4) comprise a plurality of sub memory blocks respectively. Cache memory blocks(CMB1,CMB2,CMB3,CMB4) correspond to the memory blocks. And a tag memory control part(210) reads data stored in the memory blocks or the cache memory blocks or writes data to the memory blocks or the cache memory blocks in response to the write address or the read address.

Abstract translation: 目的：提供能够同时执行数据读取操作和数据写入操作的集成电路及其方法，以增加时钟信号的工作频率。 构成：根据在时钟信号的一个周期期间输入端口和输出端口被分离并写入地址（WADD）和读取地址（RADD）的集成电路（200），存储器块（MB1，MB2 ，MB3，MB4）分别包括多个子存储器块。 高速缓冲存储器块（CMB1，CMB2，CMB3，CMB4）对应于存储器块。 并且，标签存储器控制部件（210）响应于写入地址或读取地址读取存储在存储器块或高速缓冲存储器块中的数据或将数据写入存储器块或高速缓冲存储器块。

公开(公告)号：KR1020030084029A

公开(公告)日：2003-11-01

申请号：KR1020020022503

申请日：2002-04-24

Applicant: 삼성전자주식회사

Inventor： 손교민

IPC: G11C29/00

CPC classification number: G11C29/832 ,  G11C29/80

Abstract: PURPOSE: A semiconductor memory device having a flexible redundancy system is provided, which reduces chip size penalty, and also reduces current consumption. CONSTITUTION: The semiconductor memory device(300) comprises a default array(310) of normal memory cells. A row redundant array replaces normal memory cells of a defective row of the above default array. A row redundant sense amplifier reads data from the row redundant array. A column redundant array replaces normal memory cells of a defective column of the above default array. A column redundant write driver writes data to the column redundant array. A column redundant sense amplifier reads data from the column redundant array. And a redundancy calculation and control block(360) generates a control signal required in whether to access the redundant array and in the redundant array by receiving an address and a control signal, and disables the sense amplifier of the default array while accessing the redundant array.

Abstract translation: 目的：提供一种具有灵活冗余系统的半导体存储器件，可减少芯片尺寸损失，同时降低电流消耗。 构成：半导体存储器件（300）包括正常存储器单元的默认阵列（310）。 行冗余阵列将替换上述缺省数组的缺陷行的正常存储单元。 一行冗余读出放大器从行冗余阵列中读取数据。 列冗余阵列替代上述默认数组的缺陷列的正常存储单元。 列冗余写入驱动程序将数据写入列冗余阵列。 列冗余读出放大器从列冗余阵列读取数据。 并且冗余计算和控制块（360）通过接收地址和控制信号产生是否访问冗余阵列和冗余阵列所需的控制信号，并且在访问冗余阵列时禁用默认阵列的读出放大器 。

公开(公告)号：KR100391151B1

公开(公告)日：2003-07-12

申请号：KR1020000068967

申请日：2000-11-20

Applicant: 삼성전자주식회사

Inventor： 노용환 ,  손교민

IPC: G11C11/417

CPC classification number: G11C7/1039 ,  G11C7/1072

Abstract: Disclosed is a semiconductor memory device comprising a pipeline structure having a sense amplifier responsive to a first enable signal; a data register responsive to a second enable signal for latching an output of said sense amplifier between said sense amplifier and a common data line; and a monitoring part to monitor said first and second enable signals and adapted to prevent overlapping between an enabling interval of said first enable signal and said second enable signal.

Abstract translation: 公开了一种半导体存储器件，其包括具有响应于第一使能信号的读出放大器的流水线结构; 数据寄存器，响应于第二使能信号，用于在所述读出放大器和公共数据线之间锁存所述读出放大器的输出; 以及监视部分，用于监视所述第一和第二使能信号并且适于防止所述第一使能信号的使能间隔和所述第二使能信号之间的重叠。

公开(公告)号：KR100380024B1

公开(公告)日：2003-04-18

申请号：KR1020010000331

申请日：2001-01-04

Applicant: 삼성전자주식회사

Inventor： 손교민 ,  서영호

IPC: G11C29/00

CPC classification number: G11C29/80 ,  G11C29/846

Abstract: A semiconductor memory device having redundancy with no performance penalty. The semiconductor memory device with redundancy includes a default array; a row redundant array block separated from the default array and provided with row redundant arrays for making up for a deficiency in a row direction; a column redundant array block separated from the default array and provided with column redundant arrays for making up for a deficiency in a column; a control block supplying a control signal commonly to the default array, row redundant array, and column redundant array; and a redundant calculation block for receiving address and control signals to generate a control signal necessary to the redundant array and to determine whether the redundant array is accessed, and to generate a signal to disable a sense amplifier of the default array during the redundant array access.

Abstract translation: 具有冗余的半导体存储器件，没有性能损失。 具有冗余的半导体存储器件包括默认阵列; 一行冗余阵列块，与默认阵列分开并提供行冗余阵列以弥补行方向上的不足; 一个列冗余阵列块，与默认阵列分开并提供列冗余阵列以弥补列中的不足; 向默认阵列，行冗余阵列和列冗余阵列共同提供控制信号的控制块; 以及冗余计算块，用于接收地址和控制信号以产生冗余阵列所需的控制信号并确定冗余阵列是否被访问，并且在冗余阵列访问期间产生信号以禁用缺省阵列的读出放大器 。