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公开(公告)号：KR101390340B1
公开(公告)日：2014-05-07
申请号：KR1020070092219
申请日：2007-09-11
Applicant: 삼성전자주식회사
IPC: G11C13/02
CPC classification number: G11C11/5678 , G11C11/56 , G11C13/0004
Abstract: 본발명은다중레벨메모리장치및 그동작방법을제공한다. 이장치는그 최대값보다그 최소값근방에서더 높은저항레벨의분포밀도를갖는메모리구조체를포함한다.
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公开(公告)号：KR101258268B1
公开(公告)日：2013-04-25
申请号：KR1020070075044
申请日：2007-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C13/003 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L27/228 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/147
Abstract: 비휘발성 메모리 소자의 낸드형 저항성 메모리 셀 스트링이 제공된다. 상기 셀 스트링은 비트라인 및 상기 비트라인에 직렬 접속된 복수개의 저항성 메모리 셀들을 구비한다. 상기 복수개의 저항성 메모리 셀들의 각각은 제1 내지 제3 노드들, 상기 제1 및 제2 노드들에 각각 접속된 양 단들을 갖는 히터, 상기 제2 및 제3 노드들에 각각 접속된 양 단들을 갖는 가변저항체, 및 상기 제1 노드에 접속된 제1 단자와 상기 제3 노드에 접속된 제2 단자를 갖는 스위칭 소자를 구비한다. 상기 셀 스트링의 구조체 및 제조방법 또한 제공된다.
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公开(公告)号：KR1020120136662A
公开(公告)日：2012-12-20
申请号：KR1020110055722
申请日：2011-06-09
Applicant: 삼성전자주식회사
CPC classification number: G11C8/10 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C13/0069 , G11C2013/0054 , G11C2213/75
Abstract: PURPOSE: A resistive memory device and a sensing margin trimming method are provided to improve yield by sufficiently securing sensing margin even through a property distribution of memory cells is changed. CONSTITUTION: A resistive memory device(1000) includes a memory cell array(70) and a trimming circuit(100). The memory cell array includes a plurality of resistive memory cells. A trimming circuit generates a trimming signal according to a feature distribution shift value of the resistive memory cells. The feature distribution shift is obtained by measuring the shift of a peak distribution value of a reset current for the resistive memory cells. [Reference numerals] (100) Trimming circuit; (20) Write circuit; (40) Column decoder; (50) Row decoder; (60) Array control unit
Abstract translation: 目的：提供电阻式存储器件和感测余量修整方法，以便通过充分确保感测余量，即使通过存储器单元的特性分布来改变产量。 构成：电阻式存储器件（1000）包括存储单元阵列（70）和微调电路（100）。 存储单元阵列包括多个电阻存储单元。 微调电路根据电阻性存储单元的特征分布偏移值产生微调信号。 通过测量电阻性存储单元的复位电流的峰值分布值的偏移来获得特征分布偏移。 （附图标记）（100）修整电路; （20）写电路; （40）列解码器; （50）行解码器; （60）阵列控制单元
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公开(公告)号：KR1020120100298A
公开(公告)日：2012-09-12
申请号：KR1020110019098
申请日：2011-03-03
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: H01L22/14 , H01L22/20 , H01L27/101 , H01L2924/0002 , H01L45/04 , H01L2924/00
Abstract: PURPOSE: A method for manufacturing a semiconductor device is provided to improve durability of the semiconductor device through the densification of a phase change material layer. CONSTITUTION: A wafer is prepared(S100). A memory device including a phase change material layer is formed on the wafer(S200). The wafer is Fab-out(S300). A burn-in test for the memory device is executed(S400). A thermal process for the wafer is executed in order to make the phase change material layer dense(S500). The thermal process for the wafer is executed at the temperature which is higher than crystallization temperature of the phase change material layer and is lower than melting temperature of the phase change material layer. [Reference numerals] (S100) A wafer is prepared; (S200) A memory device including a phase change material layer is formed; (S300) The wafer is Fab-out; (S400) A burn-in test is executed; (S500) The phase change material layer is closely crowded with a thermal process
Abstract translation: 目的：提供一种用于制造半导体器件的方法，以通过相变材料层的致密化来提高半导体器件的耐久性。 构成：准备晶片（S100）。 在晶片上形成包括相变材料层的存储器件（S200）。 晶圆是Fab-out（S300）。 执行存储器件的老化测试（S400）。 执行用于晶片的热处理以使相变材料层致密（S500）。 晶片的热处理在比相变材料层的结晶温度高的温度下进行，低于相变材料层的熔融温度。 （附图标记）（S100）准备晶片; （S200）形成包括相变材料层的存储器件; （S300）晶片为Fab-out; （S400）执行老化测试; （S500）相变材料层与热处理密切相关
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公开(公告)号：KR1020090120212A
公开(公告)日：2009-11-24
申请号：KR1020080046139
申请日：2008-05-19
Applicant: 삼성전자주식회사
CPC classification number: G11C5/146 , G11C13/0004 , G11C13/0038 , G11C2213/72 , H01L27/101 , H01L27/2445 , H01L27/2463 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/144
Abstract: PURPOSE: A nonvolatile memory used as a selection element is provided to increase a sensing margin by reducing base current of bipolar junction transistor. CONSTITUTION: A nonvolatile memory used as a selection element(1) includes a memory cell, a bit line, a word line, and a reverse bias circuit. The memory cell includes the bipolar transistor connected to one end of the resistance unit and resistance unit. The word line progresses with the column direction connected to the base of the bipolar transistor. A reverse bias circuit(80) approves the reverse bias between the base and the collector of the bipolar transistor. The emitter of the bipolar transistor is connected to one end of the resistance unit.
Abstract translation: 目的：提供用作选择元件的非易失性存储器，以通过降低双极结晶体管的基极电流来增加感测裕度。 构成：用作选择元件（1）的非易失性存储器包括存储单元，位线，字线和反向偏置电路。 存储单元包括连接到电阻单元和电阻单元的一端的双极晶体管。 字线在连接到双极晶体管的基极的列方向上前进。 反向偏置电路（80）批准双极晶体管的基极和集电极之间的反向偏置。 双极晶体管的发射极连接到电阻单元的一端。
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Patent Agency Ranking
公开(公告)号：KR1020090036772A
公开(公告)日：2009-04-15
申请号：KR1020070102007
申请日：2007-10-10
Applicant: 삼성전자주식회사
IPC: H01L27/02
Abstract: A semiconductor device having a resistance device and a manufacturing method thereof are provided to minimize an occupation plane dimension of a resistance device by forming a resistance device having a surface resistance higher than a resistance device of the same size formed by semiconductor material of a polycrystalline structure. A semiconductor substrate(100) includes a first circuit region(C) and a second circuit region(P). A bottom interlayer insulation film(115) is formed on a top of the semiconductor substrate having the first circuit region and the second circuit region. An isolation film(105s), a word line(110a), and a bottom resistance device(105b) are covered by the bottom interlayer insulation film. A cell diode hole(115a) is formed by patterning the bottom interlayer insulation film, and penetrates the bottom interlayer insulation film of the first circuit region. A peripheral resistance hole(115b) is formed by patterning the bottom interlayer insulation film, and penetrates the bottom interlayer insulation film of the second circuit region. A first semiconductor pattern(120a) and a second semiconductor pattern(125a) are laminated inside the cell diode hole. A wall dopant region(120b) and a top resistance device(125b) are formed inside the peripheral resistance hole.
Abstract translation: 提供一种具有电阻器件及其制造方法的半导体器件，用于通过形成表面电阻高于由多晶结构的半导体材料形成的相同尺寸的电阻器件的电阻器件来最小化电阻器件的占位面尺寸 。 半导体衬底（100）包括第一电路区域（C）和第二电路区域（P）。 在具有第一电路区域和第二电路区域的半导体衬底的顶部上形成底层间绝缘膜（115）。 隔离膜（105s），字线（110a）和底部电阻装置（105b）被底层层间绝缘膜覆盖。 通过图案化底层层间绝缘膜形成电池二极管孔（115a），并穿透第一电路区域的底层间绝缘膜。 通过图案化底层层间绝缘膜形成外围电阻孔（115b），并穿透第二电路区域的底层层间绝缘膜。 第一半导体图案（120a）和第二半导体图案（125a）层叠在单元二极管孔内。 在外围电阻孔内部形成壁掺杂剂区域（120b）和顶电阻装置（125b）。
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公开(公告)号：KR1020090011452A
公开(公告)日：2009-02-02
申请号：KR1020070075044
申请日：2007-07-26
Applicant: 삼성전자주식회사
IPC: H01L21/8247 , H01L27/115
CPC classification number: G11C13/003 , G11C11/1675 , G11C13/0004 , G11C13/0007 , G11C2213/31 , G11C2213/32 , G11C2213/71 , G11C2213/75 , H01L27/228 , H01L27/2454 , H01L27/2481 , H01L45/04 , H01L45/06 , H01L45/1233 , H01L45/126 , H01L45/147 , H01L45/141
Abstract: NAND-type resistive memory cell strings of a non-volatile memory device and methods of fabricating the same are provided to improve the degree of integration of the non-volatile memory device by forming the resistive memory cells including the variable resistibility material. The first NAND type resistive memory cell string(STR1) comprises the bit line(BL), a plurality of resistive memory cell(CL1,CL2,CL3) which is serially connected to the bit line and the main switching element(SW0). The first phase-shift memory cell(CL1) among a plurality of resistive memory cells comprises the first heater(H1), the first variable resistance(R1) and the first switching device(SW1). The second phase-shift memory cell has the same configuration as the first phase-shift memory cell.
Abstract translation: 提供了非易失性存储器件的NAND型电阻式存储单元串及其制造方法，以通过形成包括可变电阻材料的电阻式存储单元来提高非易失性存储器件的集成度。 第一NAND型电阻性存储单元串（STR1）包括位线（BL），与位线串联连接的多个电阻性存储单元（CL1，CL2，CL3）和主开关元件（SW0）。 多个电阻存储单元中的第一相移存储单元（CL1）包括第一加热器（H1），第一可变电阻（R1）和第一开关装置（SW1）。 第二相移存储单元具有与第一相移存储单元相同的配置。
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公开(公告)号：KR100689840B1
公开(公告)日：2007-03-08
申请号：KR1020050093146
申请日：2005-10-04
Applicant: 삼성전자주식회사
IPC: H01L21/336
Abstract: A method for fabricating a semiconductor device having a recessed gate electrode is provided to maintain an improved characteristic of a CMOS by avoiding poly-depletion effect while preventing voids in a cell gate electrode from transferring. A semiconductor substrate(101) is etched to form a channel trench(107). The channel trench is covered with a first semiconductor layer covering the semiconductor substrate. A second semiconductor layer is formed on the first semiconductor layer, having a lower impurity density than that of the first semiconductor layer. The channel trench includes a lower channel trench(107a) and an upper channel trench(107b). The lower trench has an inner wall profile of a substantially round type. The upper channel trench has a width smaller than the maximum width of the lower channel trench.
Abstract translation: 提供一种用于制造具有凹陷栅电极的半导体器件的方法，以通过避免多晶耗尽效应来保持CMOS的改进特性，同时防止单元栅电极中的空隙传输。 蚀刻半导体衬底（101）以形成沟道沟槽（107）。 沟道沟槽被覆盖半导体衬底的第一半导体层覆盖。 第二半导体层形成在第一半导体层上，具有比第一半导体层更低的杂质密度。 沟道沟槽包括下沟道沟槽（107a）和上沟道沟槽（107b）。 下沟槽具有大致圆形类型的内壁轮廓。 上沟道沟槽的宽度小于下沟道沟槽的最大宽度。
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公开(公告)号：KR1020010028871A
公开(公告)日：2001-04-06
申请号：KR1019990041370
申请日：1999-09-27
Applicant: 삼성전자주식회사
Inventor： 하대원
IPC: H01L21/28
CPC classification number: H01L27/1052 , H01L21/31116 , H01L21/76897 , H01L23/485 , H01L27/105
Abstract: PURPOSE: A method for forming a bit line contact hole is to concurrently form the bit line contact hole at cell array region and peripheral region by using photolithography process once. CONSTITUTION: The first conductive region(108,116a,116b), the first insulating layer(110,114) and the second insulating layer(118) having different etch ratio are disposed at the first region of a semiconductor substrate(100) and the second conductive region(105a) and the second insulating layer are disposed at the second region of the semiconductor substrate. A photoresist pattern(120) is formed on the second insulating layer. The first contact hole(122,124) exposing the second conductive region of the second region is formed at the second region and an opening(126) for the second contact hole exposing the first insulating layer of the first region is formed at the first region by selectively etching the second insulating layer on the first and second region using the photoresist pattern. The second contact hole exposing the first conductive region of the first region is formed at the first region by etching the exposed first insulating layer using the photoresist pattern.
Abstract translation: 目的：形成位线接触孔的方法是通过使用光刻工艺同时在单元阵列区域和外围区域形成位线接触孔。 构成：在半导体衬底（100）的第一区域处设置具有不同蚀刻比率的第一导电区域（108,116a，116b），第一绝缘层（110,114）和第二绝缘层（118），并且第二导电区域 （105a），并且第二绝缘层设置在半导体衬底的第二区域。 光致抗蚀剂图案（120）形成在第二绝缘层上。 暴露第二区域的第二导电区域的第一接触孔（122,124）形成在第二区域处，并且用于暴露第一区域的第一绝缘层的第二接触孔的开口（126）通过选择性地形成在第一区域 使用光致抗蚀剂图案蚀刻第一和第二区域上的第二绝缘层。 通过使用光致抗蚀剂图案蚀刻暴露的第一绝缘层，在第一区域上形成暴露第一区域的第一导电区域的第二接触孔。
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公开(公告)号：KR100238224B1
公开(公告)日：2000-01-15
申请号：KR1019960080095
申请日：1996-12-31
Applicant: 삼성전자주식회사
IPC: H01L21/28
Abstract: 금속배선과 콘택홀의 미스얼라인(Misalign)과 금속배선의 노칭(Notching) 문제를 해결할 수 있는 반도체 장치의 금속배선 형성방법에 관하여 개시하고 있다. 이를 위하여 본 발명은, W1의 폭을 갖는 금속배선이 형성될 반도체 기판에 절연막을 형성하는 단계와, 절연막의 표면을 패터닝하여 W2의 폭과 형성되는 금속배선의 저항에 따라 깊이를 달리하는 음각형태의 금속배선이 형성될 부분을 형성하는 단계와, 상기 결과물의 전면에 스페이서 형성을 위한 물질층을 증착하는 단계와, 물질층에 에치백(etch back) 공정을 진행하여 음각형태의 금속배선이 형성될 부분의 양측면에 스페이서를 형성하는 단계와, 스페이서가 형성된 반도체 기판의 전면에 콘택홀이 형성되는 영역만을 개구한 상태의 포토레지스트 패턴을 형성하는 단계와, 포토레지스트 패턴 및 물질층을 식각 마스크로 절연막을 셀프 얼라인(self align) 방식으로 식각하여 콘택홀을 형성하는 단계와, 포토레지스트 패턴을 제거하고 콘택홀을 매몰하는 도� �층을 증착하는 단계와, 도전층이 형성된 결과물의 전면을 식각하여 금속배선인 도전막을 형성하는 단계를 포함하여 구성되는 것을 특징으로 하는 반도체 장치의 금속배선 형성방법을 제공한다.
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