公开(公告)号：KR1020040038450A

公开(公告)日：2004-05-08

申请号：KR1020020067406

申请日：2002-11-01

Applicant: 삼성전자주식회사

Inventor： 배용준 ,  한공흠 ,  김상균 ,  하영남 ,  손진국

IPC: G11C29/00

Abstract: PURPOSE: A defect cell screen circuit of a semiconductor memory device and a method for the same are provided to effectively detect the defect cell since the screen is performed by reducing the pulse width margin of the word line selection signal of a conventional write mode during the defect cell screen mode. CONSTITUTION: A defect cell screen circuit of a semiconductor memory device includes a mode selection circuit(100), a data transition detector(DTD), DTD Summator Pulse signal(PPD) generation circuit(200). The mode selection circuit(100) outputs a pair of mode selection signals being opposite to each other by receiving the option signal through the option pads. The PPD pulse generation circuit(200) controls the width of the word line selection signal by the mode selection signal outputted from the mode selection circuit(100) by receiving the DTD signal.

Abstract translation: 目的：提供半导体存储器件的缺陷单元屏幕电路及其方法，以有效地检测缺陷单元，因为屏幕是通过减少常规写入模式的字线选择信号的脉冲宽度裕度来执行的 缺陷单元格屏幕模式。 构成：半导体存储器件的缺陷单元屏幕电路包括模式选择电路（100），数据转换检测器（DTD），DTD累加器脉冲信号（PPD）产生电路（200）。 模式选择电路（100）通过通过选项焊盘接收选项信号而输出彼此相反的一对模式选择信号。 PPD脉冲发生电路（200）通过接收DTD信号，通过从模式选择电路（100）输出的模式选择信号来控制字线选择信号的宽度。

公开(公告)号：KR1020010046123A

公开(公告)日：2001-06-05

申请号：KR1019990049752

申请日：1999-11-10

Applicant: 삼성전자주식회사

Inventor： 한공흠

IPC: G11C7/06

Abstract: PURPOSE: A semiconductor memory device is provided to prevent the delay of speed reading operation by ground noise. CONSTITUTION: The memory device includes a memory cell array, a plurality of sense amplifiers(12), a plurality of precharging circuits(14) and a plurality of sense amplifying drivers(20). The plurality of sense amplifiers amplify and output a data from the memory cell array in response to a sense amplifier enabling signal of the first state, The plurality of precharging circuits are connected to a pair of output lines of each of the plurality of sense amplifiers and precharge the pair of output lines in response to the sense amplifier enabling signal of the second state. The plurality of sense amplifying drivers generate a pair of output signals of the first state and a pair of complementary output signals by driving the pair of output signals from each of the plurality of sense amplifiers in response to the control signal of the first state.

Abstract translation: 目的：提供半导体存储器件，以防止地面噪声导致速度读数的延迟。 构成：存储器件包括存储单元阵列，多个读出放大器（12），多个预充电电路（14）和多个读出放大驱动器（20）。 多个读出放大器响应于第一状态的读出放大器使能信号而放大并输出来自存储单元阵列的数据。多个预充电电路连接到多个读出放大器中的每一个的一对输出线，以及 响应于第二状态的读出放大器使能信号而对一对输出线预充电。 多个感测放大驱动器响应于第一状态的控制信号，通过驱动来自多个读出放大器中的每一个的输出信号对，产生一对第一状态的输出信号和一对互补输出信号。

公开(公告)号：KR1020000015351A

公开(公告)日：2000-03-15

申请号：KR1019980035223

申请日：1998-08-28

Applicant: 삼성전자주식회사

Inventor： 한공흠 ,  박철성

IPC: H03K19/00

Abstract: PURPOSE: A semiconductor memory device is provided to decrease power consumption by preventing excessively large current from flowing through a pull down transistor of a sense amplifier of the semiconductor memory device. CONSTITUTION: Sense amplifiers(10,14) generate a sense output signal pair by amplifying difference of data from a data line pair responding to a sense amplifier enable signal. Pull up transistors(P1,P2) pull up the sense output signal pair responding to a first status of a inverted output enable signal in the case that the sense amplifier enable signal is a second status. A short pulse generator(22) generates a shot pulse responding to a second status of the inverted output enable signal in the case that the sense amplifier enable signal is a first status. Pull down transistors(N13-N16) pull down a level of the sense output signal pair to a signal level responding to the short pulse.

Abstract translation: 目的：提供半导体存储器件以通过防止过大的电流流过半导体存储器件的读出放大器的下拉晶体管来降低功耗。 构成：检测放大器（10,14）通过放大响应于读出放大器使能信号的来自数据线对的数据的差异来产生检测输出信号对。 在读出放大器使能信号为第二状态的情况下，上拉晶体管（P1，P2）将响应于反相输出使能信号的第一状态上拉检测输出信号对。 在读出放大器使能信号为第一状态的情况下，短脉冲发生器（22）产生响应于反相输出使能信号的第二状态的镜头脉冲。 拉下晶体管（N13-N16）将感测输出信号对的电平下拉到响应短脉冲的信号电平。

公开(公告)号：KR1019990060783A

公开(公告)日：1999-07-26

申请号：KR1019970081027

申请日：1997-12-31

Applicant: 삼성전자주식회사

Inventor： 한공흠 ,  박철성

IPC: G11C11/407

Abstract: 본 발명은 반도체 메모리 장치에 관한 것으로서, 더 구체적으로는 동작 전류의 감소를 위한 반도체 메모리 장치에 관한 것으로서, 셀의 데이터를 감지하여 이를 제 1 및 제 2 출력단으로 출력하기 위한 감지 증폭기와; 감지 증폭 인에이블 신호와 출력 인에이블 신호에 응답하여 상기 감지 증폭기의 출력단의 전압 레벨을 쉬프트 하기 위한 레벨 쉬프터와; 상기 레벨 쉬프터는 상기 출력 인에이블 신호가 비활성화될 때, 전류 경로를 차단하며; 상기 레벨 쉬프터를 통해 전달되는 제 1 데이터를 풀-업 하기 위한 풀-업 회로와; 상기 레벨 쉬프터를 통해 전달되는 제 2 데이터를 풀-다운하기 위한 풀-다운 회로를 포함한다. 이와 같은 회로에 의해서 입출력 포트들의 수가 증가하여도 동작 전류의 소모량을 줄일 수 있다.