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公开(公告)号：KR1020100120991A
公开(公告)日：2010-11-17
申请号：KR1020090039906
申请日：2009-05-07
Applicant: 삼성전자주식회사
CPC classification number: H03M13/455 , G06F11/1068 , G11C16/26
Abstract: PURPOSE: A memory system performing easer manipulation and a reading method thereof are provided to select eraser by repeating the reading operation in the same voltage level when error correction is impossible, thereby correcting the error by the eraser. CONSTITUTION: A memory controller reads a data from a memory in a reference voltage level(VR)(S110). If the error correction of data is impossible, an error correction circuit corrects an error of the data(S120,S125). Otherwise, the erasure decoding of the data is determined(S130). The eraser manipulator selects erasure candidates by repeating the reading operation in a reference voltage level(S140). A erasure manipulator manipulates eraser by the selected erasure candidates(S150).
Abstract translation: 目的：提供执行简易操作的记忆系统及其读取方法，以便在不可能进行纠错的情况下通过重复相同电压电平的读取操作来选择橡皮擦，从而通过橡皮擦校正错误。 构成：存储器控制器以参考电压电平（VR）从存储器读取数据（S110）。 如果数据的纠错不可能，则纠错电路校正数据的错误（S120，S125）。 否则，确定数据的擦除解码（S130）。 橡皮擦操纵器通过重复参考电压电平中的读取操作来选择擦除候选（S140）。 擦除机械手通过选择的擦除候选来操纵橡皮擦（S150）。
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公开(公告)号：KR1020100118637A
公开(公告)日：2010-11-08
申请号：KR1020090037412
申请日：2009-04-29
Applicant: 삼성전자주식회사
CPC classification number: D06F33/02 , D06F31/00 , D06F35/005 , D06F35/007
Abstract: PURPOSE: A washing machine and a control method thereof are provided to reduce the vibration by adjusting the unbalanced position, a rotating direction and an entering operation when the spin-drying operation is performed. CONSTITUTION: A control method of a washing machine is as follows. It is checked whether a first tub and a second tub perform spin-drying operations(S10), the spin-drying operations of the first and second tubs are adjusted and the vibration of the washing machine is reduced. The performing states of the spin-drying operations of the first and second tubs are checked based on whether while any one tub spin-dries, the other tub reached a spin-drying step(S14). If yes, the tub, which reached the spin-drying step later, is adjusted to perform the spin-drying operation in the opposite direction to the other tub(S15), which spin-dried first.
Abstract translation: 目的：提供一种洗衣机及其控制方法，通过在进行脱水操作时调节不平衡位置，旋转方向和进入操作来减少振动。 构成：洗衣机的控制方法如下。 检查第一桶和第二桶是否进行旋转干燥操作（S10），调节第一和第二桶的旋转干燥操作，并且减少洗衣机的振动。 基于是否在任何一个浴缸旋转干燥，另一个桶达到旋转干燥步骤（S14）时检查第一和第二桶的脱水操作的执行状态。 如果是，则调整到后来进行脱水步骤的桶，以与首先旋转干燥的另一个桶（S15）相反的方向进行脱水操作。
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公开(公告)号：KR1020100106142A
公开(公告)日：2010-10-01
申请号：KR1020090024628
申请日：2009-03-23
Applicant: 삼성전자주식회사
CPC classification number: G11C7/1006 , G11C7/1042 , G11C8/10 , G11C11/5628 , G11C11/5678 , G11C13/00 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2211/5623
Abstract: PURPOSE: A nonvolatile memory device and a memory system including the same are provided to perform an interleaving program and deinterleaving reading by storing program data according the reading period and writing period of the nonvolatile memory device. CONSTITUTION: A memory cell array(210) is connected to read/write circuit(230) through a bit line(BL). An address decoder(220) is connected to the memory cell array through a word line(WL). A reading/ writing circuit is connected to the storing circuit(240) through the data line(DL). The storing circuit is connected to the reading/ writing circuit through the data lines. The storing circuit operates in response to the control of a control logic(250).
Abstract translation: 目的：提供一种非易失性存储器件和包括该非易失性存储器件的存储器系统，以通过根据非易失性存储器件的读取周期和写入周期存储程序数据来执行交织程序和解交错读取。 构成：存储单元阵列（210）通过位线（BL）连接到读/写电路（230）。 地址解码器（220）通过字线（WL）连接到存储单元阵列。 读/写电路通过数据线（DL）连接到存储电路（240）。 存储电路通过数据线连接到读/写电路。 存储电路响应于控制逻辑（250）的控制而工作。
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公开(公告)号：KR1020100104623A
公开(公告)日：2010-09-29
申请号：KR1020090023167
申请日：2009-03-18
Applicant: 삼성전자주식회사
CPC classification number: H03M13/618 , G06F11/1012 , H03M13/13 , H03M13/353 , H03M13/3738 , H03M13/6356 , H03M13/6362
Abstract: PURPOSE: A data processing system and a code rate control scheme thereof are provided to optimize the overhead of error control coding by varying the code rate of single ECC(Error Correction Code) codec according to the property of a channel, thereby improving the reliability of a data processing system. CONSTITUTION: A data processing system comprises a memory(1000), an encoding and decoding block(2500), and a code rate control block(2600). The memory has a plurality of storage areas. The encoding and decoding block decodes the data read from an accessed storage area according to the fixed code rate. The code rate control block has code rates corresponding to the respective storage areas. The code rate control block changes the code rate corresponding to the accessed storage area which is determined by the data read from the accessed storage area and the data decoded by the encoding and decoding block.
Abstract translation: 目的：提供一种数据处理系统及其码率控制方案，以通过根据信道的性质改变单个ECC（纠错码）编解码器的码率来优化错误控制编码的开销，从而提高信道的可靠性 一个数据处理系统。 构成：数据处理系统包括存储器（1000），编码和解码块（2500）和码率控制块（2600）。 存储器具有多个存储区域。 编码和解码块根据固定码率对从访问的存储区域读取的数据进行解码。 码率控制块具有对应于相应存储区域的码率。 码率控制块改变由从所访问的存储区域读取的数据和由编码和解码块解码的数据确定的访问存储区域的码率。
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公开(公告)号：KR1020100090966A
公开(公告)日：2010-08-18
申请号：KR1020090010219
申请日：2009-02-09
Applicant: 삼성전자주식회사
CPC classification number: G11C13/00 , G11C7/1006 , G11C11/5628 , G11C13/0033 , G11C16/3427 , G11C29/00
Abstract: PURPOSE: A semiconductor memory device and a data processing method thereof are provided to improve the reliability of data by programming the state of memory cells to avoid an arrangement which causes an error. CONSTITUTION: Data to be programmed in the row and column of a nonvolatile memory is arranged according to row and column directions. The data is coded to a modulation code according to the row or column directions. A modulation coding unit(110) codes program data from a host with a modulation coding method and transmits the coded program to a nonvolatile memory device(120). The modulation coding unit decodes the read data outputted from the nonvolatile memory device and transmits the decoded data to the host. The nonvolatile memory device writes the program data supplied from the modulation coding unit on the nonvolatile memory cells of a cell array(121). The coded program data is simultaneously loaded on a page buffer(122) of the nonvolatile memory device.
Abstract translation: 目的：提供一种半导体存储器件及其数据处理方法，通过对存储器单元的状态进行编程以避免导致错误的布置来提高数据的可靠性。 构成：根据行和列方向布置要在非易失性存储器的行和列中编程的数据。 根据行或列方向将数据编码为调制码。 调制编码单元（110）使用调制编码方法对来自主机的节目数据进行编码，并将编码的节目发送到非易失性存储装置（120）。 调制编码单元对从非易失性存储器件输出的读取数据进行解码，并将解码的数据发送到主机。 非易失性存储器件将从调制编码单元提供的程序数据写入单元阵列（121）的非易失性存储单元。 编码程序数据被同时加载在非易失性存储器件的页缓冲器（122）上。
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Patent Agency Ranking
公开(公告)号：KR1020100013844A
公开(公告)日：2010-02-10
申请号：KR1020080075555
申请日：2008-08-01
Applicant: 삼성전자주식회사
CPC classification number: G11C16/10 , G11C11/5642 , G11C16/3418 , G11C16/3427
Abstract: PURPOSE: A memory device using a threshold voltage change and a method for determining a memory data thereof are provided to determine an allocation of data by changing a threshold voltage of a memory cell. CONSTITUTION: A memory cell array(110) comprises a first memory cell and a second memory cell. An estimating unit(120) predicts a threshold voltage change of the first memory cell. The estimating unit uses a data before the first memory cell is programmed and a program target threshold voltage of the first memory cell. The estimating unit generates a metric about the change of the threshold voltage of the second memory cell based on the threshold voltage change of the first memory cell. The reading unit(130) determines a data stored in the second memory cell based on a metric.
Abstract translation: 目的：提供使用阈值电压变化的存储器件和用于确定其存储器数据的方法，以通过改变存储器单元的阈值电压来确定数据的分配。 构成：存储单元阵列（110）包括第一存储单元和第二存储单元。 估计单元（120）预测第一存储单元的阈值电压变化。 估计单元使用第一存储单元被编程之前的数据和第一存储器单元的程序目标阈值电压。 估计单元基于第一存储单元的阈值电压变化产生关于第二存储单元的阈值电压的变化的度量。 读取单元（130）基于度量确定存储在第二存储器单元中的数据。
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公开(公告)号：KR1020090099757A
公开(公告)日：2009-09-23
申请号：KR1020080024930
申请日：2008-03-18
Applicant: 삼성전자주식회사
IPC: G11C29/42
CPC classification number: H03M13/2903 , G06F11/1072 , H03M13/29 , H03M13/353
Abstract: PURPOSE: A memory device and an encoding/decoding method are provided to improve error correctability and to reduce an error ratio of a critical data page. CONSTITUTION: A memory device includes a memory cell array, an internal decoder, and an external decoder(340). The internal decoder ECC(Error Control Codes) decodes a first code word(311) by applying a first decoding method selected based on the characteristic of a first channel to the first code word read from the memory cell array. The internal decoder ECC decodes a second code word(321) by applying a second decoding method selected based on the characteristic of the second channel to the second code word read from the memory cell array. The external decoder ECC decodes the ECC decoded first code word and the ECC decoded second code word by applying the external decoding method.
Abstract translation: 目的：提供存储器件和编码/解码方法，以提高错误校正能力并降低关键数据页的错误率。 构成：存储器件包括存储单元阵列，内部解码器和外部解码器（340）。 内部解码器ECC（错误控制代码）通过将从第一通道的特性选择的第一解码方法应用于从存储单元阵列读取的第一代码字来解码第一代码字（311）。 内部解码器ECC通过将从第二通道的特性选择的第二解码方法应用于从存储单元阵列读取的第二代码字来对第二代码字（321）进行解码。 外部解码器ECC通过应用外部解码方法对ECC解码的第一码字和ECC解码的第二码字进行解码。
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公开(公告)号：KR1020090083758A
公开(公告)日：2009-08-04
申请号：KR1020080009752
申请日：2008-01-30
Applicant: 삼성전자주식회사
CPC classification number: H03M13/29 , H03M13/1102 , H03M13/15 , H03M13/1515 , H03M13/152 , H03M13/19 , H03M13/23 , H03M13/2906 , H03M13/2957 , H03M13/2975 , H03M13/3738 , H03M13/6561
Abstract: A method and an apparatus for decoding concatenated code are provided to improve a decoding speed of the concatenated code using a log likelihood ratio about the output of the plurality of decoders. A log likelihood ratio about the received concatenated code is calculated(S110). A fist decoding data is generated by performing a first decoding of the reception data based on the log likelihood ratio(S120). The second decoding data is generated by performing the second decoding of the first decoding data(S130). The iterative decoding is determined based on the second decoding data(S140). If the iterative decoding of the receiving data, the log likelihood ratio is updated based on the second decoding data(S150).
Abstract translation: 提供了用于解码级联代码的方法和装置，以使用关于多个解码器的输出的对数似然比来提高级联代码的解码速度。 计算关于接收到的级联代码的对数似然比（S110）。 通过基于对数似然比对接收数据进行第一解码来生成第一解码数据（S120）。 通过执行第一解码数据的第二解码来生成第二解码数据（S130）。 基于第二解码数据确定迭代解码（S140）。 如果接收数据的迭代解码，则基于第二解码数据更新对数似然比（S150）。
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公开(公告)号：KR1020090046608A
公开(公告)日：2009-05-11
申请号：KR1020070112851
申请日：2007-11-06
Applicant: 삼성전자주식회사
CPC classification number: H03M13/2906 , G06F11/1072 , H03M13/2732
Abstract: 인코더 및 인코딩 방법이 제공된다. 본 발명의 인코더는 C 비트의 입력 비트열을 인코딩하여 C 비트의 제1 비트열을 생성하는 제1 인코더, 및 상기 제1 비트열을 M 개 수신하고, 상기 수신된 M 개의 제1 비트열의 데이터를 혼합하여 M 개의 제2 비트열을 생성하는 제2 인코더를 포함하는 것을 특징으로 하며, 이를 통해 오류 정정 가능성(error correctability)을 높인다.
셔플링, 랜더마이즈, 오류 제어 코드, 오류 정정 코드Abstract translation: 编码器和编码方法被提供。 本发明的编码器包括：第一编码器，用于编码C位输入位串以产生C位的第一位串;以及第二编码器，用于接收M个第一位串， 以及第二编码器，用于通过混合第一和第二M比特流来产生M个第二比特流，从而增强了纠错能力。
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公开(公告)号：KR1020080090730A
公开(公告)日：2008-10-09
申请号：KR1020070033912
申请日：2007-04-05
Applicant: 삼성전자주식회사 , 조지아 테크 리서치 코오포레이션
Inventor： 김동호 , 김재홍 , 조면균 , 맥라린,스티븐더블유.
CPC classification number: H03M13/1102 , H04L1/0043 , H04L1/0057
Abstract: A coding apparatus of a communication system is provided to reduce coding complexity by performing data coding using a parity check matrix containing more than 3-rd order columns. A coding apparatus of a communication system includes a matrix product calculator, a first parity codeword vector generator, and a second parity codeword vector generator. The matrix product includes multipliers(611). The first parity codeword vector generator includes a demultiplexer(613), first to L-th XOR units, first to L-th shift registers, a multiplexer(623), and a modulo counter(625). The second parity codeword vector generator includes a second multiplier(631), a first buffer(627), a second buffer(629), a first XOR unit(623), first to w-th shift registers(635-639), third to w-th multipliers(641-645), and second to w+1-th XOR units(647-651).
Abstract translation: 提供一种通信系统的编码装置，通过使用包含多于3阶的列的奇偶校验矩阵执行数据编码来降低编码复杂度。 通信系统的编码装置包括矩阵乘积计算器，第一奇偶码字矢量生成器和第二奇偶码字矢量生成器。 矩阵产品包括乘法器（611）。 第一奇偶校验码字矢量发生器包括解复用器（613），第一到第L个XOR单元，第一到第L移位寄存器，复用器（623）和模计数器（625）。 第二奇偶码字矢量发生器包括第二乘法器（631），第一缓冲器（627），第二缓冲器（629），第一异或单元（623），第一到第W移位寄存器（635-639），第三 到第w个乘法器（641-645）和第二到第w + 1个异或单元（647-651）。
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