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公开(公告)号：KR100460207B1
公开(公告)日：2004-12-08
申请号：KR1020020063139
申请日：2002-10-16
Applicant: 학교법인 포항공과대학교
IPC: H04L27/00
CPC classification number: H04L25/03878
Abstract: A look-ahead decision feedback equalizing receiver includes an equalizing block for amplifying a high-frequency component of an external data signal fed thereto in response to a first and a second input signal, to provide a first and a second equalized external data signal; a clock synthesizer for outputting sampling clocks, a timing thereof being adjusted by receiving an external clock synchronized with the external data signal; an over-sampler for over-sampling the first and the second equalized external data signal in synchronization with the sampling clocks. A MUX block for multiplexing the outputs of the over-sampler in response to outputs of the MUX block, to thereby attain decision results; and a phase detector for deciding the timing of the sampling clock by analyzing the decision results.
Abstract translation: 先行判定反馈均衡接收器包括：均衡块，用于响应于第一和第二输入信号而放大馈送给其的外部数据信号的高频分量，以提供第一和第二均衡的外部数据信号; 时钟合成器，用于输出采样时钟，其时序通过接收与外部数据信号同步的外部时钟来调整; 过采样器，用于与采样时钟同步地对第一和第二均衡的外部数据信号进行过采样。 MUX块，用于响应于MUX块的输出对过采样器的输出进行复用，从而获得判定结果; 以及相位检测器，用于通过分析判定结果来判定采样时钟的定时。
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公开(公告)号：KR100407816B1
公开(公告)日：2003-12-01
申请号：KR1020010034136
申请日：2001-06-16
Applicant: 학교법인 포항공과대학교
IPC: H03K19/00
Abstract: PURPOSE: A CMOS full-swing output driving circuit using an on-chip capacitor is provided to shorten a switching time and reduce switching noise by using charges of an on-chip capacitor. CONSTITUTION: A CMOS full-swing output driving circuit(300) is formed with an input portion(310), a capacitor charging/discharging portion(320), and a main driving portion(330). The input portion(310) receives an input signal(IN) and generates the first and the second driving signals(d,db). The first driving signal(d) is not inverted by the input signal(IN). The second driving signal(db) is inverted by the input signal(IN). The capacitor charging/discharging portion(320) receives the first and the second driving signals(d,db) and charges or discharges capacitors(C1,C2). The main driving portion(330) receives the first driving signal(d) from the input portion(310) and charges from the capacitor charging/discharging portion(320) and outputs an output signal(OUT) to an output terminal(OUT1).
Abstract translation: 目的：提供使用片上电容器的CMOS全摆幅输出驱动电路，通过使用片上电容器的电荷缩短开关时间并降低开关噪声。 构成：CMOS全摆幅输出驱动电路（300）由输入部分（310），电容器充电/放电部分（320）和主驱动部分（330）形成。 输入部分（310）接收输入信号（IN）并产生第一和第二驱动信号（d，db）。 第一驱动信号（d）不被输入信号（IN）反转。 第二驱动信号（db）被输入信号（IN）反转。 电容器充电/放电部分（320）接收第一和第二驱动信号（d，db），并对电容器（C1，C2）充电或放电。 主驱动部分330从输入部分310接收第一驱动信号d并且从电容器充电/放电部分320充电并将输出信号OUT输出到输出端子OUT1。
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公开(公告)号：KR1020030063027A
公开(公告)日：2003-07-28
申请号：KR1020020003573
申请日：2002-01-22
Applicant: 학교법인 포항공과대학교 , 삼성전자주식회사
IPC: H03L7/00
CPC classification number: H04L25/03878 , H03K5/086
Abstract: PURPOSE: A receiver for compensating the data and the skew of clock by using an equalizing technique is provided to allow a high speed signal transmission by compensating the skew between the clock and the data signal by over sampling the compensated result signal. CONSTITUTION: A receiver for compensating the data and the skew of clock by using an equalizing technique includes an equalizer(20), an over-sampler(22), a clock-data phase detector(24) and a clock synthesizer(26). In the receiver, the equalizer(20) equalizes the received data signal and the over sampler(22) compares a predetermined sampling clock with the equalized data supplied from the equalizer(20). The clock-data phase detector(24) determines the position adjustment of the sampling clock by analyzing the comparison result supplied from the over sampler(22). And, the clock synthesizer(26) generates the sampling clock by synthesizing the clock supplied from outside in response to the position adjustment determination of the clock supplied from the clock-data phase detector(24) and supplies the generated sampling clock to the over sampler(22).
Abstract translation: 目的：提供一种用于通过均衡技术补偿数据和时钟偏移的接收机，以通过对补偿结果信号进行过采样来补偿时钟与数据信号之间的偏差来实现高速信号传输。 构成：通过使用均衡技术来补偿数据和时钟偏移的接收机包括均衡器（20），过采样器（22），时钟数据相位检测器（24）和时钟合成器（26）。 在接收机中，均衡器（20）对接收到的数据信号进行均衡，过采样器（22）将预定采样时钟与从均衡器（20）提供的均衡数据进行比较。 时钟数据相位检测器（24）通过分析从过采样器（22）提供的比较结果来确定采样时钟的位置调整。 并且，时钟合成器（26）响应于从时钟数据相位检测器（24）提供的时钟的位置调整确定，合成从外部提供的时钟来产生采样时钟，并将产生的采样时钟提供给过采样器 （22）。
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Patent Agency Ranking
公开(公告)号：KR100299050B1
公开(公告)日：2001-11-01
申请号：KR1019990022914
申请日：1999-06-18
Applicant: 학교법인 포항공과대학교
IPC: H03K3/356
Abstract: 본발명은상보게이트-소스파형의절반스윙클럭구동회로와이를적용한플립플롭을개시한다. 본발명에따른상보게이트-소스파형의절반스윙클럭을적용한플립플롭은상보적으로 VDD/2의스윙폭을갖는클럭(CKNH, CKNL, CKPH, CKPL)을전류증폭감지부에있는각각의 NMOS트랜지스터(21)와 PMOS트랜지스터(41, 42)의게이트와소스에인가하여풀립플롭의트랜지스터의게이트-소스를 180도위상이상이한클럭으로상보적으로동시에구동함으로써매우낮은전력을소비하면서도완전스윙하는플립플롭과동일한지연속도를유지할수 있어, 저전력과고속의클럭시스템을갖는 CMOS VLSI 칩을구현할수 있다.
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公开(公告)号：KR1020010091311A
公开(公告)日：2001-10-23
申请号：KR1020000012842
申请日：2000-03-14
Applicant: 학교법인 포항공과대학교
IPC: H03K21/08
CPC classification number: H03K23/58 , H03K21/38 , H03K23/667
Abstract: PURPOSE: A high-speed programmable frequency demultiplier is provided to increase a frequency limit of an input clock capable of demultiplying in a demultiplier by rapidly improving an operation speed of a counter. CONSTITUTION: A high-speed programmable frequency demultiplier is comprised of a counter and a control circuit(20). The counter is comprised of six flip-flops(FF21-FF26) and a NAND gate(G21). A clock input of a flip-flop(FF21) of the least significant bit becomes a clock to be demultiplied. An output of each flip-flop constructs a counter structure in an asynchronous way. The frequency of each flip-flop output is reduced to half as it passes bit-by-bit from the least significant bit to the most significant bit. Excepting the flip-flop(FF21) of the least significant bit, every flip-flops(FF22-FF26) perform a feedback operation on an inverting output of each flip-flop to a D input terminal. The D input terminal of the flip-flop(FF21) of the least significant bit is inputted by the NAND gate(G21) calculating an output of an inverted MX1S generated in the control circuit(20) and an inverting output signal of the flip-flop(FF21) of the least significant bit.
Abstract translation: 目的：提供高速可编程分频器，通过快速提高计数器的运行速度，提高输入时钟的频率限制，从而能够降低分频器的性能。 构成：高速可编程分频器由计数器和控制电路（20）组成。 该计数器由六个触发器（FF21-FF26）和一个与非门（G21）组成。 最低有效位的触发器（FF21）的时钟输入变为要分配的时钟。 每个触发器的输出以异步方式构建计数器结构。 每个触发器输出的频率从最低有效位逐位传递到最高有效位时减少到一半。 除了最低有效位的触发器（FF21）之外，每个触发器（FF22-FF26）对每个触发器的反相输出执行到D输入端的反馈操作。 最低有效位的触发器（FF21）的D输入端由计数在控制电路（20）中产生的反相MX1S的输出和反相输出信号的NAND门（G21）输入， （FF21）的最低有效位。
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公开(公告)号：KR1020000060755A
公开(公告)日：2000-10-16
申请号：KR1019990009350
申请日：1999-03-19
Applicant: 학교법인 포항공과대학교
IPC: G06F13/38
Abstract: PURPOSE: A system for transmitting a binary-to-ternary conversion data is provided to make a high-speed data transmission by converting a ternary data to a binary data and extending a limited bandwidth. CONSTITUTION: A system for transmitting a binary-to-ternary conversion data includes an input part(200) and an output part(210). The input part(200) converts a ternary data to a binary data, a synchronizes a converted binary data to a predetermined first clock, and transmits it to the inside of the system. The output part(210) converts the transmitted binary data to the ternary data, synchronizes a converted binary data to a predetermined first clock, and outputs it to the outside. Thereby, the system extends a limited bandwidth, and makes a high-speed data transmission by converting a ternary data to a binary data.
Abstract translation: 目的：提供一种用于发送二进制到三进制转换数据的系统，通过将三进制数据转换为二进制数据并扩展有限的带宽来进行高速数据传输。 构成：用于发送二进制到三进制转换数据的系统包括输入部分（200）和输出部分（210）。 输入部分（200）将三进制数据转换为二进制数据，将转换的二进制数据同步到预定的第一时钟，并将其发送到系统内部。 输出部分（210）将发送的二进制数据转换为三进制数据，将转换的二进制数据同步到预定的第一时钟，并将其输出到外部。 因此，系统扩展有限的带宽，并且通过将三进制数据转换为二进制数据来进行高速数据传输。
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公开(公告)号：KR100184761B1
公开(公告)日：1999-04-15
申请号：KR1019960027730
申请日：1996-07-10
Applicant: 학교법인 포항공과대학교
IPC: H03K19/00
CPC classification number: H03K19/00384 , H03K19/09429
Abstract: 본 발명은 풀업 트랜지스터(M1) 및 풀다운 트랜지스터(M2)를 포함하는 CMOS 3-상태 버퍼 제어 회로에 관한 것으로서, 온도 변화에 대응한 가변 전압(Vp1),(Vd1)를 출력하는 온도 보상형 정전류원(2)과, 제어신호(C)및 데이터신호(D)를 조합하여 스위칭 신호(/PU),(PU),(/PD),(PD)를 출력하는 3 상태 제어 회로(3)와, 상기 3상태 제어 회로(3)의 스위칭 신호(/PU),(PU)에 따라 상기 가변전압(Vp1)을 상기 풀업 트랜지스터(M1)의 게이트에 인가하는 전송 게이트(TG2)와, 상기 스위칭 신호(/PU)에 따라 상기 트랜지스터(M1)의 구동을 제어하는 트랜지스터(M3)와, 상기 3 상태 제어 회로(3)의 스위칭 신호(/PD),(PD)에 따라 상기 가변 전압(Vp1)을 상기 풀다운 트랜지스터(M2)의 게이트에 인가하는 전송 게이트(TG2)와,상기 스위칭 신호(/PD)에 따라 상기트랜지스터(M2)의 구동을 제어하는 트랜지스터(M4 )를 구비한다.
즉, 본 발명은 3 상태 제어 회로에서 풀업 및 풀다운 트랜지스터의 게이트에 인가되는 전압을 온도에 따라 가변되게 하여 온도 변화에 따른 출력 I/O핀에 충전 및 방전되는 전류를 일정하게하므로써 역기전력 효과에 의한 접지 상승 및 전파 시간 지연 효과를 최소로 유지 할 수 있는 잇점이 있다.-
公开(公告)号：KR1019980012907A
公开(公告)日：1998-04-30
申请号：KR1019960027730
申请日：1996-07-10
Applicant: 학교법인 포항공과대학교
IPC: H03K19/00
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