公开(公告)号：KR100295427B1

公开(公告)日：2001-07-12

申请号：KR1019990013140

申请日：1999-04-14

Applicant: 학교법인 포항공과대학교

Inventor： 박홍준 ,  심재윤

IPC: H03K19/0175

CPC classification number: H03K19/018578 ,  H03K19/018592

Abstract: 본발명은고속으로동작하는전류모드임피던스가정합된양방향버퍼회로를개시한다. 본발명에따른동일한입출력버퍼를내장한외부칩과신호를양방향으로전송하는전류모드입출력버퍼는, 상기외부칩으로전송하고자하는송신신호(IN1)과상기외부칩으로부터수신되는송신신호(IN2)의평균전류값(I1)을평균전압으로변환하여출력하는송수신평균전압출력부(210); 상기송신신호(IN1)의전압레벨에따라선택적으로생성된소정의기준전류값(Iref)을기준전압으로변환하는기준전압출력부(220); 상기송수신평균전압출력부와상기기준전압출력부에서생성한전압을비교하여상기외부칩으로부터전송된수신신호에상응된로직신호를출력하는비교기(230); 및상기외부칩에접속된전송선의특성임피던스와같도록바이어스전압을생성하여상기각 출력부에공급하는바이어스전압생성부를포함함을특징으로한다. 본발명에의한임피던스가정합된전류모드양방향입출력버퍼는하나의전송선로를이용하여칩과칩간에고속으로데이터전송을수행하며, 칩의공정변화에도안정적인특성을갖는양방향입출력버퍼를제공한다.

公开(公告)号：KR100377064B1

公开(公告)日：2003-06-02

申请号：KR1019950007824

申请日：1995-04-04

Applicant: 학교법인 포항공과대학교

Inventor： 박홍준 ,  심재윤

IPC: H03F3/187

Abstract: PURPOSE: A fully differential folded cascode CMOS OP amplifier having an adaptive bias circuit and a common mode feedback circuit are provided to form a high-speed OP amplifier by using a digital CMOS process. CONSTITUTION: A common mode detector provides an output voltage signal proportional to a common mode voltage which is extracted by a common mode reference signal in response to the first input signal, the second input signal, and a common mode reference voltage. The common mode detector includes a plurality of nMOS input terminal differential amplifiers(82,84), a plurality of pMOS input terminal differential amplifier(86,88), and a push-pull CMOS amplifier. The nMOS input terminal differential amplifiers and the pMOS input terminal differential amplifier are used for providing the first and the second current outputs proportional to the common mode voltage. The push-pull CMOS amplifier is used for converting the first and the second current outputs to output voltage signals.

公开(公告)号：KR1019960039601A

公开(公告)日：1996-11-25

申请号：KR1019950007824

申请日：1995-04-04

Applicant: 학교법인 포항공과대학교

Inventor： 박홍준 ,  심재윤

IPC: H03F3/187

Abstract: 본 발명의 새로운 적응 바이어스 회로 및 공통 모드 궤한 회로를 이용한 차동 폴디드 캐스코드 CMOS OP AMP 장치는 종래의 폴디드 캐스코드 CMOS OP AMP 회로에 부착가능한 적응 바이어스 회로를 제안하여 직류 전력 소모 및 직류 전압 이득을 크게 유지하면서도 슬루속도를 크게 증가시켜 OP AMP 장치의 고속 동작을 실현할 수 있고, 공통 모드 궤한 회로의 입력 전압의 범위를 크게 함으로써 전체 OP AMP 장치의 선형 출력 전압 범위를 극대화할 수 있으며, 또한 문턱 전압이 큰 디지털 CMOS 공정을 이용하여 4V 이하의 단일 공급 전압에서도 직류 전압 이득이 매우 크고 빠른 안정 시간을 갖도록 함으로써 저전압용 디지털 회로와 함께 동일 집적회로 칩상에 아나로그 신호 처리용 CMOS OP AMP 회로를 추가할 수 있도록 한 것이다.

公开(公告)号：KR100681944B1

公开(公告)日：2007-02-12

申请号：KR1020050108840

申请日：2005-11-15

Applicant: 학교법인 포항공과대학교 ,  포항공과대학교 산학협력단

Inventor： 심재윤

IPC: H03M7/00 ,  H03M7/40 ,  H04L12/20

Abstract: A segmented group inversion encoding method for parallel data transmission is provided to minimize a switching noise in single ended parallel data transmission by performing inversion encoding of the group. A segmented group inversion encoding method for parallel data transmission includes the steps of: initializing all flag bits to a specific value when the k number of data groups transmitted from a transmission terminal to a receiving terminal are included, and one data group of the transmitted data groups includes data bit and the other groups of the transmitted data groups include the data bit and the flag bit; outputting original data of the one data group having the data bit only through corresponding pins without encoding; and if the data group includes first to k-th groups, and the one data group having the data bit only is the k-th group, performing inversion encoding of the i-th group according to a number difference of zero and one of the i-th group, and a number difference of total zero and one of the encoded i+1th to k-1th groups and k-th group.

Abstract translation: 提供了用于并行数据传输的分段组反转编码方法，以通过执行该组的反转编码来最小化单端并行数据传输中的开关噪声。 用于并行数据传输的分段组反转编码方法包括以下步骤：当包括从发送终端发送到接收终端的k个数据组时，将所有标志位初始化为特定值，并且发送数据的一个数据组 组包括数据比特，并且其他组的发送数据组包括数据比特和标志比特; 仅通过相应引脚输出具有数据比特的一个数据组的原始数据而不进行编码; 并且如果数据组包括第一组到第k组，并且具有仅数据比特的一个数据组是第k组，则根据零和第一组中的一个的数量差对第i组执行反转编码 第i组，以及编码的第i + 1至第k-1组和第k组中的总零和一个之间的数量差。

公开(公告)号：KR1020000066203A

公开(公告)日：2000-11-15

申请号：KR1019990013140

申请日：1999-04-14

Applicant: 학교법인 포항공과대학교

Inventor： 박홍준 ,  심재윤

IPC: H03K19/0175

CPC classification number: H03K19/018578 ,  H03K19/018592

Abstract: PURPOSE: A current-mode bidirectional input/output buffer is provided to make a bidirectional transmission by using one transmission for transmitting data between two chips. CONSTITUTION: A current-mode bidirectional input/output buffer includes a transmitting/receiving average voltage output part(210), a reference voltage output part(220), a comparator(230), and a bias voltage generator. The transmitting/receiving average voltage output part(210) converts average current value between a transmission signal(IN1) and a transmission signal(IN2) to average voltage. The transmission signal(IN1) is transmitted to the external chip. The transmission signal(IN2) is received from external chip. The reference voltage output part(220) converts a predetermined reference current(Iref) to a reference voltage. The reference current(Iref) is selectively generated. The comparator(230) compares a voltage of the output part(210) with a voltage of the output part(220), and outputs a logic signal corresponding to a receiving signal from the external chip. The bias voltage generator generates a bias voltage to be identical with a characteristic impedance of a transmission line connected to the external chip, and provides it to each output part.

Abstract translation: 目的：提供电流模式双向输入/输出缓冲器，通过使用一个传输在两个芯片之间传输数据进行双向传输。 构成：电流模式双向输入/输出缓冲器包括发射/接收平均电压输出部分（210），参考电压输出部分（220），比较器（230）和偏置电压发生器。 发送/接收平均电压输出部分210将发送信号（IN1）和发送信号（IN2）之间的平均电流值转换为平均电压。 发送信号（IN1）被发送到外部芯片。 从外部芯片接收发送信号（IN2）。 参考电压输出部分（220）将预定的参考电流（Iref）转换为参考电压。 选择性地产生参考电流（Iref）。 比较器（230）将输出部分（210）的电压与输出部分（220）的电压进行比较，并从外部芯片输出与接收信号相对应的逻辑信号。 偏置电压发生器产生与连接到外部芯片的传​​输线的特性阻抗相同的偏置电压，并将其提供给每个输出部分。

公开(公告)号：KR1020000060755A

公开(公告)日：2000-10-16

申请号：KR1019990009350

申请日：1999-03-19

Applicant: 학교법인 포항공과대학교

Inventor： 박홍준 ,  심재윤

IPC: G06F13/38

Abstract: PURPOSE: A system for transmitting a binary-to-ternary conversion data is provided to make a high-speed data transmission by converting a ternary data to a binary data and extending a limited bandwidth. CONSTITUTION: A system for transmitting a binary-to-ternary conversion data includes an input part(200) and an output part(210). The input part(200) converts a ternary data to a binary data, a synchronizes a converted binary data to a predetermined first clock, and transmits it to the inside of the system. The output part(210) converts the transmitted binary data to the ternary data, synchronizes a converted binary data to a predetermined first clock, and outputs it to the outside. Thereby, the system extends a limited bandwidth, and makes a high-speed data transmission by converting a ternary data to a binary data.

Abstract translation: 目的：提供一种用于发送二进制到三进制转换数据的系统，通过将三进制数据转换为二进制数据并扩展有限的带宽来进行高速数据传输。 构成：用于发送二进制到三进制转换数据的系统包括输入部分（200）和输出部分（210）。 输入部分（200）将三进制数据转换为二进制数据，将转换的二进制数据同步到预定的第一时钟，并将其发送到系统内部。 输出部分（210）将发送的二进制数据转换为三进制数据，将转换的二进制数据同步到预定的第一时钟，并将其输出到外部。 因此，系统扩展有限的带宽，并且通过将三进制数据转换为二进制数据来进行高速数据传输。