公开(公告)号：KR1020080106754A

公开(公告)日：2008-12-09

申请号：KR1020070054584

申请日：2007-06-04

Applicant: 한국과학기술원

Inventor： 유회준 ,  김주영

IPC: G06F9/06 ,  G06T1/00

CPC classification number: G06F9/06 ,  G06T1/00

Abstract: An arithmetic calculation apparatus for image filtering for accelerating the image filtering and convolution calculation in a microprocessor is presented to accelerate the image filtering process rapidly, by making smooth data transfer during window transfer. According to an arithmetic calculation apparatus of a microprocessor, a booth encoder(10) performs booth encoding, in order to perform multiplication independently by distributing image data inputted to the microprocessor in a register of the microprocessor in the unit of image pixel length for image filtering according to an SOP command. A CSA tree(20) performs multiplication by adding sub-sums performed independently by being distributed in the booth encoder. An accumulation part(30) accumulates multiplication result performed by being distributed through the CSA tree.

Abstract translation: 提出了一种用于加速微处理器中的图像滤波和卷积计算的图像滤波的算术计算装置，通过在窗口传送期间进行平滑的数据传输，快速加速图像滤波处理。 根据微处理器的算术计算装置，展位编码器（10）执行展位编码，以通过以图像像素长度为单位将输入到微处理器的图像数据分配到微处理器的寄存器中来独立地进行乘法 根据SOP命令。 CSA树（20）通过分配在展台编码器中独立执行的子和进行乘法运算。 累积部分（30）累积通过CSA树分发的乘法结果。

公开(公告)号：KR1020170054672A

公开(公告)日：2017-05-18

申请号：KR1020150157104

申请日：2015-11-10

Applicant: 한국과학기술원

Inventor： 김상욱 ,  김봉훈 ,  김주영

IPC: C08J7/00 ,  C08F297/08 ,  H01L29/06

Abstract: 본발명은 a) 블록공중합체와결점용융제를혼합하여혼합물을제조하는단계; b) 상기혼합물을기판상에도포하여박막을형성하는단계; 및 c) 상기박막을어닐링하여자기조립하는단계;를포함하는결점용융을이용한자기조립나노패턴형성방법으로상기결점은χN이 10.5 이하인결점용융을이용한자기조립나노패턴형성방법에관한것이다.

Abstract translation: 本发明提供了一种制备嵌段共聚物的方法，该方法包括：a）将嵌段共聚物和缺陷熔体混合以制备混合物; b）将该混合物施加到基底上以形成薄膜; 和c）退火和自组装薄膜。缺陷是使用χN为10.5或更小的缺陷熔化的自组装纳米图案形成方法。

公开(公告)号：KR1020130138399A

公开(公告)日：2013-12-19

申请号：KR1020120061924

申请日：2012-06-11

Applicant: 한국과학기술원

Inventor： 김상욱 ,  신동옥 ,  김봉훈 ,  김주영

IPC: C08J5/18 ,  C08L53/00 ,  C08F297/08 ,  B32B15/08

CPC classification number: G03F7/0002

Abstract: A method for manufacturing a mixed block copolymer thin film, a method for manufacturing a mixed block copolymer template, and the mixed block copolymer thin film and template manufactured thereby are provided. The method for manufacturing a mixed block copolymer thin film according to the present invention comprises: a step for making mixed liquid by mixing a first block copolymer which is self-assembled with high molecular weight and long length of chain and a second block copolymer which is symmetric and which has lower molecular weight and shorter length than the first block copolymer low molecular weight; a step of forming a block copolymer thin film by laminating the mixed liquid; and a step for self-assembling by heat treating the block copolymer thin film. [Reference numerals] (AA) Existing technique;(BB) Present invention

Abstract translation: 提供混合嵌段共聚物薄膜的制造方法，混合嵌段共聚物模板的制造方法以及由此制造的混合嵌段共聚物薄膜和模板。 根据本发明的制备混合嵌段共聚物薄膜的方法包括：通过混合自组装的高分子量和长链长度的第一嵌段共聚物和第二嵌段共聚物来制备混合液的步骤， 对称且具有比第一嵌段共聚物低分子量更低的分子量和更短的长度; 通过层压混合液形成嵌段共聚物薄膜的步骤; 以及通过热处理嵌段共聚物薄膜进行自组装的步骤。 （附图标记）（AA）现有技术;（BB）本发明

公开(公告)号：KR101069602B1

公开(公告)日：2011-10-05

申请号：KR1020090092515

申请日：2009-09-29

Applicant: 한국과학기술원

Inventor： 유회준 ,  오진욱 ,  김주영

IPC: G06F15/16 ,  G06F9/06 ,  G06F9/38 ,  G06J3/00

Abstract: 또한, 물체인식시스템에있어서는전체입력영상의글로벌특징인물체의관심영역을뉴로-퍼지시스템이빨리찾아내고, 이를기반으로고성능병렬처리프로세서로선택된영역에한해서물체의로컬특징을추출하는자세한이미지를처리함으로써, 영상처리속도의가속화, 저면적, 및저 전력으로실시간물체인식을가능하게한다.

公开(公告)号：KR1020110024132A

公开(公告)日：2011-03-09

申请号：KR1020090082013

申请日：2009-09-01

Applicant: 한국과학기술원

Inventor： 유회준 ,  김주영

IPC: H04L12/28

CPC classification number: H04L49/109 ,  H04L49/254

Abstract: PURPOSE: A multicast network on chip, a system thereof, and a network switch are provided to minimize total cycle number and energy necessary for data transmission. CONSTITUTION: A packet includes a header flit, an address flit, and a data flit. The header flit includes routing information with bit values which is respectively mapped with a last IP. A switch router includes a first variable strength driver which is connected to an output terminal of a first input buffer for changing transmission strength when transmitting a packet which is buffered in a first input buffer(111). A first arbiter selects a plurality of upper output port according to a first grant signal and enables a packet which is buffered in the input buffer to be transmitted to the selected upper output port at the same time.

Abstract translation: 目的：提供片上组播网络，其系统和网络交换机，以最小化数据传输所需的总周期数和能量。 构成：一个数据包包括一个头部flit，一个地址flit和一个数据flit。 头部flit包括具有分别与最后IP映射的比特值的路由信息​​。 交换路由器包括第一可变强度驱动器，其连接到第一输入缓冲器的输出端，用于在发送缓冲在第一输入缓冲器（111）中的分组时改变传输强度。 第一仲裁器根据第一授权信号选择多个上输出端口，并且使得缓冲在输入缓冲器中的分组同时被发送到所选择的上输出端口。

公开(公告)号：KR1020110018558A

公开(公告)日：2011-02-24

申请号：KR1020090076066

申请日：2009-08-18

Applicant: 한국과학기술원

Inventor： 유회준 ,  김주영

IPC: H04L12/44 ,  G06F9/46 ,  G06F13/00

CPC classification number: Y02D10/14 ,  H04L49/109

Abstract: PURPOSE: A network on chip system is provided to apply a new combining topology about a data communication of a multi core processor having a plurality of IP(Internet Protocol). CONSTITUTION: A network on chip and a network on chip system are comprised as follows. A plurality of IPs are divided into a plurality of groups comprised of a fixed IP and connect each IP group to a star topology with a plurality of local switch router as a center. A plurality of local switch routers is connected with a star topology method by at least one upper switch router as a center. At this time, each layer is comprised of a vertical structure and a swich route comprising the same layer is comprised of a ring topology structure. These hierarchical structures bring an effect which increases the total band width. Also, the system can minimize data communication performance time and energy consumption.

Abstract translation: 目的：提供一种片上系统以应用关于具有多个IP（因特网协议）的多核处理器的数据通信的新的组合拓扑。 构成：片上网络和芯片上网系统如下。 将多个IP划分为由固定IP组成的多个组，并将每个IP组连接到具有多个本地交换路由器作为中心的星形拓扑。 多个本地交换路由器由至少一个上层交换路由器作为中心与星形拓扑方法连接。 此时，每个层由垂直结构构成，并且包括相同层的swich路由由环形拓扑结构组成。 这些分层结构带来了增加总带宽的效果。 此外，系统可以最大限度地减少数据通信的性能时间和能耗。

公开(公告)号：KR1020090030022A

公开(公告)日：2009-03-24

申请号：KR1020070095306

申请日：2007-09-19

Applicant: 한국과학기술원

Inventor： 유회준 ,  김주영

IPC: G06F17/16 ,  G06F17/00

CPC classification number: G06F17/30483 ,  G06F17/16

Abstract: A method of vector quantization and a computer program electronic recording medium for the method are provided in order to reduce the operation quantity for the vector quantization by detecting the element sum total range of vector having the query and minimum distance. A method of vector quantization performs the followings: the element sum total is included in a segment, and is analyzed; all vectors of the segment block in which the element sum total is included and distance of the query vector save; the minimum distance value at the segment block is set up as the arbitrary minimum distance value; the vector quantization is performed from the segment including the value in which the arbitrary minimum distance value is reduced in the element sum total of the query vector about the database section of segment including the value adding the element sum total and arbitrary minimum distance value of the query vector; and the element sum total range of vector having the query vector and minimum distance is detected.

Abstract translation: 提供了一种用于该方法的矢量量化方法和计算机程序电子记录介质，以通过检测具有查询和最小距离的向量的元素和总范围来减少矢量量化的操作量。 矢量量化的方法执行以下操作：元素总和包含在段中，并进行分析; 包含元素总和的段块的所有向量和查询向量保存的距离; 将段块处的最小距离值设置为任意的最小距离值; 从包括在关于数据库部分的查询向量的元素总和中减去任意最小距离值的值的段执行向量量化，该数据库段包括添加元素和总和的任意最小距离值 查询向量; 并且检测到具有查询向量和最小距离的向量的元素总和范围。

公开(公告)号：KR1020080105838A

公开(公告)日：2008-12-04

申请号：KR1020070053921

申请日：2007-06-01

Applicant: 한국과학기술원

Inventor： 유회준 ,  김주영

IPC: G06F7/00

CPC classification number: G06F7/4833 ,  G06F7/57

Abstract: An arithmetic apparatus of a microprocessor is provided to integrate the common region between an integral operation part and a log operation part for special operation such as multiplication, division or root operation so as to be mutually shared. An arithmetic apparatus of a microprocessor comprises the followings. A log converter CLZ, a shifter, a LOG-APP, a CSA tree and an ALU are respectively formed as one block. The shifter, CSA tree and ALU blocks which are commonly formed at a log data path and an integer data path are shared, and an MUX(11~16) establishes an operation path in a block, shared by a control signal of the microprocessor, at the input/output terminals of the shared blocks. The ALU block comprises an internal register for storing the operated results.

Abstract translation: 提供了一种微处理器的运算装置，用于将集成操作部分和对数操作部分之间的公共区域整合，以进行诸如乘法，除法或根操作的特殊操作，以便相互共享。 微处理器的运算装置包括以下。 对数转换器CLZ，移位器，LOG-APP，CSA树和ALU分别形成为一个块。 通常在日志数据路径和整数数据路径上形成的移位器，CSA树和ALU块被共享，并且MUX（11〜16）建立由微处理器的控制信号共享的块中的操作路径， 在共享块的输入/输出端。 ALU块包括用于存储操作结果的内部寄存器。