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公开(公告)号：US20210408980A1
公开(公告)日：2021-12-30
申请号：US16917325
申请日：2020-06-30
Applicant: Apple Inc.
Inventor： Saihua Lin , Hongrui Wang , Sohrab Emami-Neyestanak
Abstract: The present disclosure relates to systems and methods for operating transceiver circuitry to transmit or receive signals on various frequency ranges. To do so, a transmitter or a receiver of the transceiver circuitry is selectively coupled to or uncoupled from an antenna of the transceiver circuitry. Additionally, radio frequency filters may be individually or collectively coupled to and/or uncoupled from the antenna to filter different frequencies in the transmitting or receiving signals.
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公开(公告)号：US11211906B1
公开(公告)日：2021-12-28
申请号：US16917325
申请日：2020-06-30
Applicant: Apple Inc.
Inventor： Saihua Lin , Hongrui Wang , Sohrab Emami-Neyestanak
Abstract: The present disclosure relates to systems and methods for operating transceiver circuitry to transmit or receive signals on various frequency ranges. To do so, a transmitter or a receiver of the transceiver circuitry is selectively coupled to or uncoupled from an antenna of the transceiver circuitry. Additionally, radio frequency filters may be individually or collectively coupled to and/or uncoupled from the antenna to filter different frequencies in the transmitting or receiving signals.
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公开(公告)号：US20210391843A1
公开(公告)日：2021-12-16
申请号：US17234027
申请日：2021-04-19
Applicant: Apple Inc.
Inventor： Hongrui Wang , Sohrab Emami-Neyestanak , Saihua Lin
Abstract: A radio frequency filtering circuitry includes a first inductor, a second inductor, and a conductive loop. The first inductor receives a first current that induces a second current in the second inductor upon receiving the first current. The first inductor and/or the second inductor induce a third current in the conductive loop. The conductive loop adjusts the third current to reduce a first gain peak of an output signal to correlate to a second gain peak of the output signal.
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公开(公告)号：US10720892B1
公开(公告)日：2020-07-21
申请号：US16248730
申请日：2019-01-15
Applicant: Apple Inc.
Inventor： Hongrui Wang , Sohrab Emami-Neyestanak
Abstract: A Wilkinson Combiner circuit is disclosed. The circuit includes first and second input ports, and a resistive-capacitive (RC) network coupled there between. The circuit further includes an amplifier having an amplifier input node, and a coupled inductor. The coupled inductor includes first, second, and third terminals, coupled to the first input port, the second input port, and the amplifier input node, respectively. Signals conveyed from the first and second input ports are passed through the corresponding portions of the coupled inductor, are combined into a composite signal and amplified by the amplifier.
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公开(公告)号：US20240357734A1
公开(公告)日：2024-10-24
申请号：US18474880
申请日：2023-09-26
Applicant: Apple Inc.
Inventor： Behzad Biglarbegian , Hongrui Wang , Abbas Komijani , Reetika K Agarwal
CPC classification number: H05K1/0243 , H01P3/08 , H05K2201/10015 , H05K2201/1003 , H05K2201/10075
Abstract: An electronic device may include a transceiver with a substrate and an inductor on the substrate. A ring of ground traces may surround the inductor. Circuit components may be patterned onto the substrate overlapping the inductor, a region of the substrate surrounded by the inductor, and/or a region of the substrate between the inductor and the ring. The components may be arranged in trees with feed lines extending radially outward from a central axis. The components in each tree may be separated from the capacitors in other trees by gaps, preventing eddy currents on the trees. The components may be used to form bypass capacitors for power supply lines, a low-dropout regulator load, part of the loop filter of a phase-locked loop, or other portions of the transceiver. The components may thereby be used to convey signals while also meeting fill factor requirements associated with fabrication of the substrate.
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Patent Agency Ranking
公开(公告)号：US20240039564A1
公开(公告)日：2024-02-01
申请号：US18484265
申请日：2023-10-10
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Xinhua Chen
IPC: H04B1/04
CPC classification number: H04B1/04 , H04B2001/0408
Abstract: Embodiments presented herein provide apparatus and techniques to reduce a direct current (DC) voltage offset between a transmitter and receiver. Embodiments include a shared reference voltage signal generated by a reference voltage source. The receiver may include a first unit gain buffer to receive a reference voltage signal from the reference voltage source. The transmitter may be communicatively coupled to the receiver via one or more connections and may include a second unit gain buffer communicatively coupled to the first unit gain buffer via one of the connections. An amplifier (e.g., an operation amplifier) of the transmitter may include multiple positive inputs coupled to the second unit gain buffer and an offset tracker. The offset tracker may compensate for a DC offset caused by at least a power supply and/or a ground bounce.
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47.发明授权公开(公告)号：US11881715B2
公开(公告)日：2024-01-23
申请号：US17751482
申请日：2022-05-23
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani
CPC classification number: H02J50/005 , H01F27/027 , H01F27/2804 , H02J50/12 , H01F2027/2809
Abstract: An electronic device may include wireless circuitry having a transformer adjustable between first, second, and third modes. The transformer may have first, second, third, and fourth inductors. The third inductor may be magnetically coupled to the first and second inductors with equal coupling constants. The fourth inductor may be magnetically coupled to the first and second inductors with inverse coupling constants. First and second adjustable capacitors coupled to the third and fourth inductors may receive control signals that place the transformer into a selected one of the first, second, or third modes. In the first mode the transformer exhibits a passband that overlaps first and second bands. In the second mode, the transformer passes signals in the second band while filtering interference in the first band. In the third mode, the transformer passes signals in the first band while filtering interference in the second band.
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公开(公告)号：US20240022209A1
公开(公告)日：2024-01-18
申请号：US18359593
申请日：2023-07-26
Applicant: Apple Inc.
Inventor： Abbas Komijani , Hongrui Wang , Sohrab Emami-Neyestanak
CPC classification number: H03B5/1228 , H03B5/1212 , H03B5/1271 , H03B5/1265 , H03B5/1243 , H03B5/04 , H03L7/097 , H03L7/099 , H03L7/0891
Abstract: An electronic device may include a transceiver with mixer circuitry that up-converts or down-converts signals based on a voltage-controlled oscillator (VCO) signal. The transceiver circuitry may include first, second, third, and fourth VCOs. Each VCO may include a VCO core that receives a control voltage and an inductor coupled to the VCO core. Fixed linear capacitors may be coupled between the VCO cores. A switching network may be coupled between the VCOs. Control circuitry may place the VCO circuitry in one of four different operating modes and may switch between the operating modes to selectively control current direction in each of the inductors. The VCO circuitry may generate the VCO signal within a respective frequency range in each of the operating modes. The VCO circuitry may exhibit a relatively wide frequency range across all of the operating modes while introducing minimal phase noise to the system.
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49.发明公开公开(公告)号：US20230403014A1
公开(公告)日：2023-12-14
申请号：US18447221
申请日：2023-08-09
Applicant: Apple Inc.
Inventor： Reetika K. Agarwal , Abbas Komijani , Hongrui Wang
CPC classification number: H03L7/0891 , H03C3/0941 , H03L7/099 , H04L7/033 , H03L7/185 , H03L7/1976 , H03L7/091
Abstract: An electronic device may include wireless circuitry having mixer circuitry configured to receive oscillator signals from a partial-fractional phase-locked loop (PLL). The partial-fractional PLL may include a phase frequency detector, a charge pump, a loop filter, and a frequency divider connected in a loop. To implement the partial-fractional capability of the PLL, the frequency divider may receive a bitstream from a first order sigma delta modulator and a finite impulse response filter. The first order sigma delta modulator may output a periodic non-randomized output. The finite impulse response filter may increase the frequency of toggling of the periodic non-randomized output. Configured and operated in this way, the partial-fractional PLL can exhibit reduced phase noise.
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公开(公告)号：US11824593B2
公开(公告)日：2023-11-21
申请号：US17941975
申请日：2022-09-09
Applicant: Apple Inc.
Inventor： Hongrui Wang , Abbas Komijani , Saihua Lin , Sohrab Emami-Neyestanak
IPC: H04B17/21 , H04B17/345 , H03B5/18
CPC classification number: H04B17/21 , H03B5/1829 , H04B17/345 , H04B2215/065
Abstract: An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.
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