公开(公告)号：IT1304670B1

公开(公告)日：2001-03-28

申请号：ITTO980831

申请日：1998-10-05

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  BALISTRERI EMANUELE

IPC: G05F3/24 ,  G05F3/26 ,  H03F1/30 ,  H03L7/089

公开(公告)号：IT1303209B1

公开(公告)日：2000-10-30

申请号：ITTO981018

申请日：1998-12-03

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  BALISTRERI EMANUELE

IPC: G05F3/24 ,  H01L21/8238 ,  H01L27/02 ,  H01L27/092 ,  H03B5/04 ,  H03F1/30 ,  H03K19/003

Abstract: A device (DC) is provided for compensating process and operating parameters variations in a CMOS integrated circuit. The device comprises means (CP, CT) for generating a first and a second compensation signals which depend on quality indexes of the fabrication process of the P and N transistors of the integrated circuit and on the operating temperature, and which are capable of compensating deviations of the controlled quantity from the desired value, due to the deviation of the quality indexes and temperature, respectively, from a typical value which would originate the desired value for the output parameter. The compensating device also can be implemented in the form of CMOS integrated circuit, preferably jointly with the device (OS) to be subjected to compensation.

公开(公告)号：CA2292042A1

公开(公告)日：2000-06-11

申请号：CA2292042

申请日：1999-12-10

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BALISTRERI EMANUELE ,  BURZIO MARCO

IPC: H03L7/099 ,  H03L7/10 ,  H03L7/107 ,  H03L7/097

Abstract: A phase locked loop comprising an input comparator capable of generating a deviation signal which is used for driving an oscillator so as to generate an output signal locked to the input signal. The oscillator operates according to a plurality of characteristics under the control of control means comprising searching means arranged to carry out a first search phase by scanning the family of characteristics admitted for the operation of the oscillator by bands of progressively reduced width, according to a general, dichotomic procedure. Upon completion of this first search phase, additional means of fine search are destined to identify the optimum operating point, compensating possible fluctuations of the characteristics.

公开(公告)号：ITTO980831A1

公开(公告)日：2000-04-05

申请号：ITTO980831

申请日：1998-10-05

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  BALISTRERI EMANUELE

IPC: G05F3/24 ,  G05F3/26 ,  H03F1/30 ,  H03L7/089

公开(公告)号：IT1281028B1

公开(公告)日：1998-02-11

申请号：ITTO950914

申请日：1995-11-13

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  PELLEGRINO PAOLO

IPC: H03M9/00 ,  H04L7/08 ,  H04J3/04 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04

Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.

公开(公告)号：ITTO950914A1

公开(公告)日：1997-05-13

申请号：ITTO950914

申请日：1995-11-13

Applicant: CSELT CENTRO STUDI LAB TELECOM

Inventor： BURZIO MARCO ,  PELLEGRINO PAOLO

IPC: H04L7/08 ,  H03M9/00 ,  H04J3/04 ,  H04L12/56 ,  H04Q3/00 ,  H04Q11/04

Abstract: The serializing-parallelizing circuit comprises, on a single integrated circuit chip (IC), a transmitter (TX) which performs the parallel-to-series conversion of the data stream, the insertion into the serial stream, with a pre-set periodicity, of a synchronism word, and the line coding of the serial stream, and a receiver (RX) in which clock signals synchronous with the data stream are extracted from a serial stream of coded data and in which the data are decoded and the decoded signals undergo series-to-parallel conversion. The transmitter (TX) and the receiver (RX) can be configured to operate with 4 or 8-bit parallelism.