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公开(公告)号：JPH10117033A
公开(公告)日：1998-05-06
申请号：JP11862297
申请日：1997-04-23
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO , LUKA PESAND
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H01S3/133
Abstract: PROBLEM TO BE SOLVED: To provide a drive circuit allowing drive light sources of both conduction types and allowing operation not substantially depending on a manufacturing process. SOLUTION: This circuit consists of a bias and modulation current generator and a pair of control voltage sources to this bias and modulation current generator. The control voltage sources B, M obtain a control voltage pair from a drive current. The generator which the light source LA requires can be selected by an outside signal by using control logic and a CMOS gate. This circuit can be prepared by using three pads consisting of an integrated circuit. As these pads, there are those having respective control voltage sources B, M and the thirds D consisting of the current generator, the MOS gate and the control logic.
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2.发明专利
公开(公告)号：JPH1091578A
公开(公告)日：1998-04-10
申请号：JP21547897
申请日：1997-07-28
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO
Abstract: PROBLEM TO BE SOLVED: To provide a device and a method to secure the time alignment of two digital signals which are substantially isochronal to each other. SOLUTION: Plural (2 ) pieces of replicas CK1 to CK4 are produced for a 1st signal CKIN having a given phase difference, and the replicas CK3 and CK4 are sampled (4, 5) in response to the rise edge of a 2nd signal DATA. A combination of logical signals is obtained through the above sampling and shows the phase relation between each of replicas CK1 to CK4 and the signal DATA. The output signal CKOIJT of this device is aligned with the signal DATA and corresponds to one of replicas CK1 to CK4 of the signal CKIN that reproduces best the desired alignment condition.
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公开(公告)号：CA2212292C
公开(公告)日：2001-10-16
申请号：CA2212292
申请日：1997-07-30
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BURZIO MARCO , BOSTICA BRUNO , PELLEGRINO PAOLO
Abstract: A device and a method for aligning in time two essentially isochronous digit al signals are provided, in which a plurality (2n) of replicas (CK1-CK4) of the first s ignal (CKIN), separated by a given phase difference, are generated and a number of said re plicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of lo gic signals (SL0, SL1) is obtained which is representative of the phase relation existin g between each of said replicas (CK1-CK4) and the second signal (DATA). The output sig nal (CKOUT) of the device, aligned with the second signal, corresponds to the on e, among the replicas (CK1-CK4) of the first signal, which best reproduces the desire d alignment condition.
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公开(公告)号：IT1284718B1
公开(公告)日：1998-05-21
申请号：ITTO960665
申请日：1996-07-31
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BOSTICA BRUNO , BURZIO MARCO , PELLEGRINO PAOLO
Abstract: A device and a method for aligning in time two essentially isochronous digital signals are provided, in which a plurality (2 ) of replicas (CK1-CK4) of the first signal (CKIN), separated by a given phase difference, are generated and a number of said replicas (CK3, CK4) is subjected to sampling (4, 5) in correspondence with the rising edges of the second signal (DATA). As the result of the sampling, a combination of logic signals (SLO, SL1) is obtained which is representative of the phase relation existing between each of said replicas (CK1-CK4) and the second signal (DATA). The output signal (CKOUT) of the device, aligned with the second signal, corresponds to the one, among the replicas (CK1- CK4) of the first signal, which best reproduces the desired alignment condition.
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公开(公告)号：DE69500311T2
公开(公告)日：1997-10-02
申请号：DE69500311
申请日：1995-06-05
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA VALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
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Patent Agency Ranking
公开(公告)号：DE687046T1
公开(公告)日：1996-11-28
申请号：DE95108625
申请日：1995-06-05
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA VALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
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公开(公告)号：ITTO940462D0
公开(公告)日：1994-06-06
申请号：ITTO940462
申请日：1994-06-06
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA WALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
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公开(公告)号：CA2203489A1
公开(公告)日：1997-10-24
申请号：CA2203489
申请日：1997-04-23
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： PELLEGRINO PAOLO , PESANDO LUCA , BURZIO MARCO , BOSTICA BRUNO
IPC: H01L27/092 , H01L21/8238 , H01S5/042 , H01S5/068 , H01S5/40 , H04B10/04 , H04B10/06 , H04B10/142 , H04B10/152 , H01S3/10
Abstract: A high speed drive circuit for optical sources. The circuit comprises bias and modulation current generators for both p-type and n-type optical sources, and a pair of control voltage sources for controlling the bias and modulation current generators, which obtain pairs of control voltages from an adjustable driving current. The circuit includes control logic and CMOS gates for selecting between the p-type and n-type generators by means of an external signal. The circuit is fabricated as an integrated circuit having three pads, one for each control voltage source and the third pad comprises the current generators, the CMOS gates and the control logic circuit.
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公开(公告)号：DE69500311D1
公开(公告)日：1997-06-26
申请号：DE69500311
申请日：1995-06-05
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA VALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
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公开(公告)号：CA2150656A1
公开(公告)日：1995-12-07
申请号：CA2150656
申请日：1995-05-31
Applicant: CSELT CENTRO STUDI LAB TELECOM
Inventor： BELLA VALTER , PELLEGRINO PAOLO
Abstract: The circuit in CMOS technology allows high speed driving of optical sources, in particular laser diodes, operating efficiently at speeds that meet the requirements imposed by optical fibre communication systems and avoiding interference between driving currents and biasing current in the optical source. The circuit comprises a bias current generator, a modulation current generator and a cascade of CMOS inverter stages that supplies a driving voltage to the modulation current generator and receives digital signals at its input. It is possible to independently adjust the bias current, so as to allow driving sources with different threshold currents, and to adjust the modulation current.
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