公开(公告)号：CA980911A

公开(公告)日：1975-12-30

申请号：CA193154

申请日：1974-02-21

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HO IRVING T ,  PRICER WILBUR D

公开(公告)号：CA963162A

公开(公告)日：1975-02-18

申请号：CA191791

申请日：1974-02-05

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

公开(公告)号：CA960775A

公开(公告)日：1975-01-07

申请号：CA145358

申请日：1972-06-22

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G06F11/10 ,  G11C29/00

Abstract: A computer memory, most particularly a monolithic memory, may be constructed of components which contain defective bit cells. During the production process, the monolithic chips are sorted into groups in accordance with the chip sector which contains one or more defective cells. The chips are then mounted on memory cards, with all of the chips having a defect in a given chip sector being mounted on a corresponding card sector. The cards, each of which is produced in a substantially identical manner, are then assembled into a complete memory. The address wiring of the memory is provided in such a manner as to ensure that no given memory word, or defined group of bits within a memory word, contains within it more than one memory cell that is known or suspected to be defective. Means are also provided for deriving from the address of any given memory word the bit location within said word of a defective or suspicious bit. In one embodiment shown herein, the suspect bit is bypassed in favor of a redundant bit provided within the memory system. In another embodiment described herein, the suspect bit is utilized just as if it were a good bit, but, upon detection of an error, the suspect bit will be presumed to be in error.

公开(公告)号：CA945677A

公开(公告)日：1974-04-16

申请号：CA137076

申请日：1972-03-14

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  BROWN DAVID T ,  WALKER ERNEST L

IPC: G06F7/78 ,  G11C19/08

Abstract: This specification discloses a bubble domain memory in which data is arranged for immediacy of access in accordance with its last use. The memory comprises a plurality of parallel shift registers in which data can be accessed in parallel. In other words, each of the shift registers contains a bit of a page or word so that by the performance of one shifting operation all of the bits of the page or word can be accessed. Data in each shift register is arranged in its order of last use so that the access position K of a shift register having K bit positions contains the last bit of information used and the position K-1 preceding the access position K in the shift register contains the bit of data used just previously to the data in the access position K and so on. In these shift registers the shift positions are arranged in loops for shifting the data between the positions of the shift register. Two such loops are provided, one of the loops contains all the shift positions so that data in any position in the shift register can be shifted into the access position K of the register for reading or writing. The other loop contains all the positions of the shift register but the access position K. This second loop is for reordering the data in the shift register in order of last use after data has been shifted into the access position K for reading or writing by the first loop.

公开(公告)号：CA918808A

公开(公告)日：1973-01-09

申请号：CA68269

申请日：1969-11-25

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F

IPC: G06F13/10 ,  G06F13/40

公开(公告)号：CA773732A

公开(公告)日：1967-12-12

申请号：CA773732D

Applicant: IBM

Inventor： BEAUSOLEIL WILLIAM F ,  HILL PETER R ,  SMITH RONALD M ,  IV WILLIAM A CLARK

公开(公告)号：CA757766A

公开(公告)日：1967-04-25

申请号：CA757766D

Applicant: IBM

Inventor： PADEGS ANDRIS ,  CALVERT JAMES D ,  BEAUSOLEIL WILLIAM F