公开(公告)号：BR9002875A

公开(公告)日：1991-08-20

申请号：BR9002875

申请日：1990-06-18

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F15/00 ,  G06F1/04 ,  G06F1/12 ,  G06F1/24 ,  G06F11/00

Abstract: A microprocessor based computer system is provided which includes a reset circuit having a phase error detector for detecting a phase error between an initial reset signal and a clock signal provided to the microprocessor clock input. The reset circuit further includes a phase error corrector for adjusting the phase of the clock signal if a phase error is detected so as to substantially minimize the phase error. The reset circuit includes a reset signal regenerator for providing a new reset signal to the reset input of the microprocessor when the phase of the clock signal is adjusted.

公开(公告)号：BR9002554A

公开(公告)日：1991-08-13

申请号：BR9002554

申请日：1990-05-30

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  MILLING PHILIP E

IPC: G06F12/08 ,  G06F9/00

Abstract: A dual bus microcomputer system including a cache subsystem improves performance under certain circumstances by allowing programmable control over the LOCK function. More particularly, additional logic is coupled between the LOCK output of the CPU and the LOCK input of the cache controller. A control bit from an I/O port is a second input to the additional logic. With the control bit in one state, the logic allows the LOCK input to follow the LOCK output. In the other state of the control bit, the LOCK input is disabled regardless of the state of the LOCK output.

公开(公告)号：CA2018065A1

公开(公告)日：1990-12-19

申请号：CA2018065

申请日：1990-06-01

Applicant: IBM

Inventor： BEGUN RALPH M

IPC: G06F13/36 ,  G06F12/00 ,  G06F12/02 ,  G06F13/28 ,  G06F13/42

Abstract: A data processing system includes a microprocessor operable in a burst mode to read data from a memory. The memory, its controller and bus are operable in a pipelining mode. Array logic is connected between the microprocessor and the remaining elements for converting the burst mode to the pipeline mode.

公开(公告)号：CA2016399A1

公开(公告)日：1990-11-30

申请号：CA2016399

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.