公开(公告)号：CA2016399A1

公开(公告)日：1990-11-30

申请号：CA2016399

申请日：1990-05-09

Applicant: IBM

Inventor： BEGUN RALPH M ,  BLAND PATRICK M ,  DEAN MARK E

IPC: G06F12/02 ,  G06F12/08

Abstract: The capacity of cache memory supported by a cache controller can be increased by offsetting the relationship between CPU address output terminals and address input terminals of the cache controller and correspondingly doubling the cache line size. In some cases, additional logic generates a hidden memory cycle so as to fetch from memory that number of bytes equal to the new line size regardless of the width of the data bus. The hidden memory cycle is initiated by a read miss and further logic generates a memory address which is not generated by the CPU. The hidden memory cycle is maintained transparent to the CPU and cache controller by inhibiting the change in a READY signal until completion of both the normal memory cycle and the hidden memory cycle.

公开(公告)号：CA1226623A

公开(公告)日：1987-09-08

申请号：CA458355

申请日：1984-07-06

Applicant: IBM

Inventor： BLAND PATRICK M ,  BOLT WILLIAM H

IPC: H02J1/00 ,  G06F1/00 ,  G06F1/32 ,  G06F3/02 ,  G06F3/023

Abstract: POWER CONSERVATION SYSTEM IN BATTERY . POWERED KEYBOARD DEVICE INCLUDING MICROPROCESSOR In a self-contained battery powered keyboard entry device, the keyboard is driven from a microprocessor and its output sensed by the microprocessor to generate drive signals for an infra-red transmitter. The sense lines are monitored so that, on a key depression, the microprocessor is switched to an operating mode from its low-power standby mode. When all sensed signals have been processed and outputted, the microprocessor is returned to the low-power standby mode.