公开(公告)号：CA2437661A1

公开(公告)日：2002-09-06

申请号：CA2437661

申请日：2002-02-25

Applicant: IBM

Inventor： HOENICKE DIRK ,  BLUMRICH MATTHIAS A ,  HEIDELBERGER PHILIP ,  CHEN DONG ,  TAKKEN TODD E ,  GIAMPAPA MARK E ,  GARA ALAN G ,  COTEUS PAUL W ,  VRANAS PAVLOS M ,  STEINMACHER-BUROW BURKHARD D

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/16 ,  G06F15/173 ,  G06F15/177 ,  G06F15/76 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G06F15/00 ,  H04M1/64

Abstract: A system and method for enabling high-speed, low-latency global tree communications among processing nodes interconnected according to a tree network structure. The global tree network (100) optimally enables collectiv e reduction operations to be performed during parallel algorithm operations executing in a computer structure having a plurality of the interconnected processing nodes. Router devices (200) are included that interconnect the nodes of the tree via links to facilitate performance of low-latency global processing operations at nodes of the virtual tree and sub-tree structures. The global operations include one or more of: global broadcast operations downstream from a root node (110) to leaf nodes (120) of a virtual tree, global reduction operations upstream from leaf nodes to the root node (110) in the virtual tree, and point-to-point message passing from and any node to th e root node (110) in the virtual tree. One node of the virtual tree network is coupled to and functions as an I/O node for providing I/O functionality with an external system for each node of the virtual tree. The global tree networ k (100) may be configured to provide global barrier and interrupt functionalit y in asynchronous or synchronized manner. Thus, parallel algorithm processing operations, for example,employed in parallel computing systems, may be optimally performed in accordance with certain operating phases of the parallel algorithm operations. When implemented in a massively-parallel supercomputing structure, the global tree network (100) is physically and logically partitionable according to needs of a processing algorithm.

公开(公告)号：CA2437657A1

公开(公告)日：2002-09-06

申请号：CA2437657

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  GARA ALAN G ,  COTEUS PAUL W

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  G11B20/18 ,  H03M13/09 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  G08C25/00 ,  H03M13/00

Abstract: A fault isolation technique for checking the accuracy of data packets transmitted between nodes of a parallel processor (10). An independent CRC i s kept of all data sent from one processor to another. At the end of each checkpoint, the CRCs are compared. If they do not match, there was an error. The CRCs may be cleared and restarted at each checkpoint. In the preferred embodiment, the basic functionality is to calculate a CRC of all packet data that has been successfully transmitted across a given link. This CRC is done on both ends of the link, thereby allowing an independant check on all data believed to have been correctly transmitted. Preferably, all links have this CRC coverage, and the CRC used in this link level check is different from th at used in the packet transfer protocol. This independent check, if successfull y passed, virtually eliminateds the possibility that any data errors were miss ed during the previous transfer period.

公开(公告)号：CA2436413A1

公开(公告)日：2002-09-06

申请号：CA2436413

申请日：2002-02-25

Applicant: IBM

Inventor： CHEN DONG ,  COTEUS PAUL W ,  HEIDELBERGER PHILIP ,  GARA ALAN G ,  GIAMPAPA MARK E ,  BLUMRICH MATTHIAS A ,  BHANOT GYAN V ,  TAKKEN TODD E ,  VRANAS PAVLOS M ,  STEINMACHER-BUROW BURKHARD D

IPC: G06F11/10 ,  G06F9/46 ,  G06F9/52 ,  G06F11/00 ,  G06F11/20 ,  G06F12/00 ,  G06F12/02 ,  G06F12/08 ,  G06F12/10 ,  G06F13/00 ,  G06F13/24 ,  G06F13/38 ,  G06F15/173 ,  G06F15/177 ,  G06F15/80 ,  G06F17/14 ,  H04L1/00 ,  H04L7/02 ,  H04L7/033 ,  H04L12/28 ,  H04L12/56 ,  H04L25/02 ,  H05K7/20 ,  H04L1/18 ,  H04J3/02

Abstract: Class network routing is emplemented in a network such as a computer network comprising a plurality of parallel compute processors at nodes (Q00-Q22) thereof. Class network routing allows a compute processor to broadcast a message to a range (one or more) of other compute processors in the computer network, such as processors in a column or a row. Normally this type of operation requires a separate message to be sent to each processor. With cla ss network routing pursuant to the invention, a single message is sufficient, which generally reduces the total number of messages in the network as well as the latency to do a broadcast. Class network routing is also applied to dens e matrix inversion algorithms on distributed memory parallel supercomputers (Fig. 1) with hardware class function (multicast) capability. This is achiev ed by exploiting the fact that the communication patterns of dense matrix inversion can be served by hardware classe functions, which results in faste r execution times.