DYNAMIC LINE TERMINATING CLAMPING CIRCUIT

    公开(公告)号:JPH11330944A

    公开(公告)日:1999-11-30

    申请号:JP6927499

    申请日:1999-03-15

    Applicant: IBM

    Abstract: PROBLEM TO BE SOLVED: To attain the fast bus pumping by placing a 2nd transistor TR between a 2nd reference voltage and an intermediate node and only the 1st and 2nd inverters connected to each other between the intermediate node and a 1st TR and between the intermediate node and the control input of the 2nd TR respectively. SOLUTION: The inverters 40 and 42 have the switching voltage threshold of about 0.7 VDD and about 0.3 VDD respectively. Therefore, a transistor TR 32 is turned off when the signal voltage level rises up to 0.7 VDD at a terminating node 30. In the same way, a TR 36 is turned on when the signal voltage level dropped down to 0.3 VDD at an intermediate node 30 and then turned off when the signal voltage rises higher than 0.3 VDD. The node 30 is clamped at VSS by the operations of both TR 32 and 36 when a driver 24 drives a signal line 22 at a high logical level.

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