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    47.
    发明专利
    未知

    公开(公告)号：DE1000619B

    公开(公告)日：1957-01-10

    申请号：DEI0009605

    申请日：1954-12-30

    Applicant: IBM DEUTSCHLAND

    Inventor： HENLE ROBERT A

    IPC: H03K3/286 ,  H03K3/30

    Abstract: 765,382. Transistor two stable state circuit. INTERNATIONAL BUSINESS MACHINES CORPORATION. Dec. 21, 1954 [Dec. 31, 1953], No. 37381/54. Class 40(6) In a trigger circuit producing one output pulse for every other input pulse, a two stable state circuit 1 and blocking oscillator 2 are cross-coupled from the output of one to the input of the other so that the oscillator changes over the two stable state circuits on alternate input pulses. A resistor 15 between collector 1c and emitter 1e gives positive feed-back to a transistor of the type described in U.S.A. Specification 2,609,428, having a rectifying base contact. Assuming transistor 1 to be off, the low collector potential is effective over resistor 30 to bias off the emitter 2e of the blocking oscillator transistor 2. A positive pulse applied over blocking capacitor 24 is ineffective to trigger the oscillator 2 but is fed over capacitor 7 and biased diode 8 to raise the emitter potential and thus cause transistor 1 to pass to the on state. The rise in collector potential raises the emitter potential of transistor 2 so that the next pulse is effective to trigger the blocking oscillator. The output pulse from winding 26 is negative and is applied over diode 28 to reset transistor 1 in preparation for the next input pulse. Pulses at half the input frequency appear at terminals 32, 33 and a square wave at terminals 16, 17, Fig. 3 (not shown). In a modification, Fig. 2 (not shown) a conventional point contact transistor is employed in the two stable state circuit with a biased diode as load in the base circuit.

    ERROR DETECTION AND CORRECTION SYSTEM
    49.
    发明专利
    ERROR DETECTION AND CORRECTION SYSTEM 未知

    公开(公告)号：CA942427A

    公开(公告)日：1974-02-19

    申请号：CA127433

    申请日：1971-11-12

    Applicant: IBM

    Inventor： BOSSEN DOUGLAS C ,  HENLE ROBERT A ,  HSIAO MU Y ,  PRICER W DAVID ,  MALEY GERALD A

    IPC: G06F11/10 ,  G11C29/00

    Abstract: Errors in parallel binary data produced by a plurality of data track, e.g., a plurality of parallel shift registers, are corrected by a system in which the shift registers which are stuck, i.e., inalterable, are determined and counted. By single Hamming error detection means, the presence of a Hamming error and an indication of the bit position of a single Hamming error is made. Comparison means determine if the indicated Hamming error is coincident with a stuck track. Then, dependent on the parity condition of the data as well as the count of stuck tracks, apparatus is provided for complementing one or more of the stuck tracks and/or correcting the indicated Hamming error.

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