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公开(公告)号：AT63395T
公开(公告)日：1991-05-15
申请号：AT83111128
申请日：1983-11-08
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).
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公开(公告)号：BR8701783A
公开(公告)日：1988-02-02
申请号：BR8701783
申请日：1987-04-14
Applicant: IBM
Inventor： EGGENBERGER JOHN SCOTT , PATEL ARVIND MOTIBHAI
Abstract: Methods and apparatus for implementing PRML codes are disclosed. Specifically considered in detail are rate 8/9, constrained codes having run length limitation parameters (0, 4/4) and (0, 3/6) are provided for any partial response (PR) signalling system employing maximum likelihood (ML) detection.
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公开(公告)号：ZA838482B
公开(公告)日：1984-10-31
申请号：ZA838482
申请日：1983-11-14
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).
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公开(公告)号：ZA837725B
公开(公告)日：1984-08-29
申请号：ZA837725
申请日：1983-10-17
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A syndrome processing unit for a multibyte error correcting system includes logical circuitry for performing product operation on selected pairs of 8-bit syndrome bytes, and exclusive-OR operations on selected results of the product operations are selectively combined to define usable cofactors that correspond to coefficients of the error locator polynomial if the codeword contains less than the maximum number of errors for which the system has been designed.
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公开(公告)号：ZA8307725B
公开(公告)日：1984-08-29
申请号：ZA8307725
申请日：1983-10-17
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
CPC classification number: H03M13/151 , G11B20/1833
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Patent Agency Ranking
公开(公告)号：NO840715L
公开(公告)日：1984-08-29
申请号：NO840715
申请日：1984-02-24
Applicant: IBM
Inventor： PATEL ARVIND MOTIBHAI
Abstract: A two-level multibyte error correcting system for correcting up to t, one-byte errors in a codeword in response to processing 2t, non-zero syndrome bytes at the first level and up to t 2 one-byte errors in a codeword in response to processing 2t 2 non-zero syndrome bytes at the second level when processing said 2t, syndrome bytes at said first level does not produce an all zero pattern for said 2t 2 syndrome bytes. The system is particularly applicable to data handling devices such as disk files, where in a relatively long block of data may be divided into subblocks, each of which may contain up to t, - x one-byte errors that are correctable at the first level by processing 2t, non-zero syndrome bytes. One identifiable subblock of the word may contain up to t, + x one-byte errors which are correctable by processing said 2t 2 non-zero syndrome bytes where 0 ≤ x 2 - t 1 ).
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公开(公告)号：DE2532149A1
公开(公告)日：1976-03-04
申请号：DE2532149
申请日：1975-07-18
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: This specification describes an error correction system for a high density memory made up of a number of monolithic wafers each containing a plurality of arrays that are addressed thru circuitry and wiring contained on that wafer. The storage bits on the wafers are functionally divided into a number of blocks each containing a plurality of words. The words of each block are on several wafers with each word made up of a plurality of arrays on a single array wafer. Each word in a block is protected by a similar error correction double multiple error detection code. The block is further protected by two additional check words made up using a b-adjacent code. Each byte in the check words protects one byte position of the words of the block. When a single error is detected in any word by the SEC-MED code the code corrects the error. If a multiple error is detected, the multiple error signal points to the word in error to be corrected by the b-adjacent code check words.
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公开(公告)号：DE2425823A1
公开(公告)日：1975-01-02
申请号：DE2425823
申请日：1974-05-28
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HONG SE JUNE , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: Errors in code words fetched from memory or utilized in some other device are detected by apparatus distributed throughout the memory and then corrected. Illustratively, a 72-bit parallel code word, comprising a 64-bit information portion and an 8-bit check portion is fetched from the memory. The check bit generator consists of 8 identical modular units which, in the case of use in a memory, can be located at different locations within the memory. The identical modular units are connected in accordance with connections determined by an H matrix. The H matrix is partitioned into eight equal sections associated with eight information bits forming a byte and a single check bit. The rows of each partition or section are cyclically permutated from section to section. For example, the first row of the first section becomes the second row of the second section, etc. Each partition of the H matrix contains the same number of 1's and each row within a partition is part of a different code group. Each of the identical modular arrangements contains a logic circuit grouping. The input information byte bits are connected to the circuits of the logic grouping so as to produce as circuit outputs the parities of the part of the code groups in the partition or section associated with the module. The identical modular units also contain circuitry to receive the partial code groups parities from the other modular units concerned with the same code group. These partial code group parities and the partial code group parity of the respective module are combined to provide the check bit for the particular module. The partial code group parity outputs from the module are transmitted to the successive other modules to form the partial code group parity inputs for the respective modules. After the information has been utilized such as writing in storage, the information bits and check bits are read into an error detector which compares the check bits generated from the received information bits with the received check bits. An error locator analyzes any mismatch to determine the location of an error. An error corrector then corrects any information or check bit which is identified as incorrect by the error locator. The error detector can consist of the same identical modular units as the check bit generator.
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公开(公告)号：DE2421112A1
公开(公告)日：1975-01-02
申请号：DE2421112
申请日：1974-05-02
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , HSIAO MU-YUE , PATEL ARVIND MOTIBHAI
Abstract: 1440285 Error correction INTERNATIONAL BUSINESS MACHINES CORP 24 April 1974 [4 June 1973] 18002/74 Heading G4A Data is stored on a plurality of independently accessible storage units, e.g. magnetic tape cartridges, and check bits, each of which is a function of a corresponding bit from each data storage unit, are stored on a check unit which may be used, in the event of a catastrophic loss of data on one of the data storage units and detected by an error checking facility associated with that unit, to restore the data on that unit. Extension of the system to include more than one check unit, each of which stores the check bits for one position of a Hamming code, is also mentioned. In normal operation, one of the data storage units is selected and data thereon is updated by read before write heads 15, 21. The difference e jk between each old bit and the corresponding new bit is EXORed with the corresponding old parity bit p k from the check unit to update the parity bits. The parity bits are initially recorded by successively (or simultaneously) reading the data storage units to record the modulo 2 sums of the corresponding bits, and data restoration is similar reading from the good data storage units and the check unit.
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公开(公告)号：DE2364788A1
公开(公告)日：1974-06-27
申请号：DE2364788
申请日：1973-12-27
Applicant: IBM
Inventor： MCDONALD JUN EARL GEORGE , PATEL ARVIND MOTIBHAI
Abstract: Error detection is enhanced by using multiple independent error codes combined with nonlinear changes in the data field as applied to different error codes. Such nonlinear permutations increase the probability of detecting errors thereby maximizing the utilization of check bit redundancies. In a magnetic tape subsystem, error detection and correction can be enhanced by scrambling track-to-error code relationships between a plurality of independent codes. Tracks with the highest probability of errors, i.e., the outside tracks on a 1/2 inch tape, for example, are connected to nonadjacent inputs of error correction code apparatus. Additionally, the input-to-track relationship of various code apparatus can be scrambled, either permanently or during a tape transducing operation. The above permutations provide best advantage with selected error correction codes and systems having identifiable probability of error patterns.
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