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公开(公告)号：JPH11353244A
公开(公告)日：1999-12-24
申请号：JP11065099
申请日：1999-04-19
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , MCLAUGHLIN CHARLES ANDREW , DANNY MARVIN NEIL , NICHOLSON JAMES OTTO , THURBER STEVEN MARK
Abstract: PROBLEM TO BE SOLVED: To prevent damage due to a bus error in loading operation or storing operation through the identification of a device which encountered an error before by using forcible illegal data parity or 0-byte enabling. SOLUTION: Device select lines from respective I/O devices 132 and 134 are connected individually to a PCT host bridge 124 and if an error occurs on a PCI(peripheral component interconnect) bus, the device number of the faulty device is recorded in an error register 204. Following loading operation and storing operation are suspended until the error register is reset and until the device number of the object device is checked in the error register. If the object device got out of order before, the completion of the loading/storing operation on the device is stopped by forcing the illegal parity or setting all of byte enabling to zero. The I/O devices activate their device select lines when the illegal parity of 0-byte enabling is forced to answer a load request or store request, but accept no store data.
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公开(公告)号：SG44390A1
公开(公告)日：1997-12-19
申请号：SG1996000087
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69026743T2
公开(公告)日：1996-11-07
申请号：DE69026743
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：BR9001125A
公开(公告)日：1991-03-05
申请号：BR9001125
申请日：1990-03-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：DE69127416D1
公开(公告)日：1997-10-02
申请号：DE69127416
申请日：1991-06-21
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , HSIAO MU-YUE , MULLIGAN JAMES MICHAEL
Abstract: A single width bidirectional bar code exhibiting inherent self clocking characteristics is provided so as to be particularly useful in the identification of semiconductor wafers in very large scale integrated circuit manufacturing processes. The codes described herein are robust, reliable and highly readable even in the face of relatively high variations in scanning speed. The codes are also desirably dense in terms of character representations per linear measurements, an important consideration in semiconductor manufacturing wherein space on chips and wafers is at a premium. Additionally, a preferred embodiment of the present invention exhibits a minimum number for the maximum number of spaces between adjacent bars in code symbol sequences.
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Patent Agency Ranking
公开(公告)号：DE69026743D1
公开(公告)日：1996-06-05
申请号：DE69026743
申请日：1990-02-02
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO , LO TIN-CHEE
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means for fixing the output of one of the memory units at a fixed value in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach to the generation of forced hard errors nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：BR9001126A
公开(公告)日：1991-03-05
申请号：BR9001126
申请日：1990-03-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：AU4939990A
公开(公告)日：1990-09-13
申请号：AU4939990
申请日：1990-02-09
Applicant: IBM
Inventor： BLAKE ROBERT MARTIN , BOSSEN DOUGLAS CRAIG , CHEN CHIN-LONG , FIFIELD JOHN ATKINSON , KALTER HOWARD LEO
Abstract: In a memory system comprising a plurality of memory units (10) each of which possesses unit-level error correction capabilities (20) and each of which are tied to a system level error correction function (30), memory reliability is enhanced by providing means (Fig. 2) for disabling the unit-level error correction capability, for example, in response to the occurrence of an uncorrectable error in one of the memory units. This counter-intuitive approach which disables an error correction function nonetheless enhances overall memory system reliability since it enables the employment of the complement/recomplement algorithm which depends upon the presence of reproducible errors for proper operation. Thus, chip level error correction systems, which are increasingly desirable at high packaging densities, are employed in a way which does not interfere with system level error correction methods.
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公开(公告)号：GB1279793A
公开(公告)日：1972-06-28
申请号：GB125571
申请日：1971-01-11
Applicant: IBM
Inventor： BOSSEN DOUGLAS CRAIG
Abstract: 1279793 Error-correcting systems INTERNATIONAL BUSINESS MACHINES CORP 11 Jan 1971 [12 Feb 1970] 1255/71 Heading G4A From a block of data comprising K bytes (D 1 , D 2 , ... D K ) each of b bits, two check bytes C 1 and C 2 are computed from the relationships C 1 = ID 1 + 1D 2 + ... +ID K C 2 =A 1 D 1 +A 2 D 2 + ... + A K D K where I is the identity element and A 1 to A K are distinct non-zero elements of Galois Field (2 b ), (the indicated multiplication and addition being Galois Field defined operations), and a decoder recovers the data from the transmitted data and check bytes without error when any number of bits are in error in any single received byte. The decoder may compute two syndrome bytes S1 and S2 each of b bits from the relationships S1 = ID 1 1 + ID 2 1 + ... + ID K 1 + IC 1 1 S2 = A 1 D 1 1 + A 2 D 2 1 + ... + A K D K 1 + IC 2 1 the primes denoting a received byte, and correction of the jth byte is indicated by the zero condition of a correction criterion B j = A j S 1 + IS 2 correction being effected by adding S 1 to the jth byte. Computation of check bits, syndrome bits and error criteria are performed using parallel adders.
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公开(公告)号：AT409996T
公开(公告)日：2008-10-15
申请号：AT00311661
申请日：2000-12-22
Applicant: IBM
Inventor： BARNETT BARRY STANLEY , BOSSEN DOUGLAS CRAIG
IPC: G06F13/10 , H04L12/24 , G06F13/00 , G06F15/177
Abstract: A method and system for problem determination and fault isolation in a storage area network (SAN) is provided. A complex configuration of multi-vendor host systems, FC switches, and storage peripherals are connected in a SAN via a communications architecture (CA). A communications architecture element (CAE) is a network-connected device that has successfully registered with a communications architecture manager (CAM) on a host computer via a network service protocol, and the CAM contains problem determination (PD) functionality for the SAN and maintains a SAN PD information table (SPDIT). The CA comprises all network-connected elements capable of communicating information stored in the SPDIT. The CAM uses a SAN topology map and the SPDIT are used to create a SAN diagnostic table (SDT). A failing component in a particular device may generate errors that cause devices along the same network connection path to generate errors. As the CAM receives error packets or error messages, the errors are stored in the SDT, and each error is analyzed by temporally and spatially comparing the error with other errors in the SDT. If a CAE is determined to be a candidate for generating the error, then the CAE is reported for replacement if possible.
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