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公开(公告)号：DE10126310A1
公开(公告)日：2002-12-19
申请号：DE10126310
申请日：2001-05-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： TAEUBER ANDREAS , DORTU JEAN-MARC , SCHMOELZ PAUL , FEURLE ROBERT
IPC: H01L23/498 , H01L23/50 , H05K3/32
Abstract: A circuit board device (14) has a number of circuit board pads (19) for joining the circuit board device to the memory chip (12), in which the circuit board pads are arranged at least in one columnar arrangement, a number of data terminals for data-input and data-output, in which the data terminals are arranged in at least two columnar arrangements, which preferably extend mainly parallel to the arrangement of the circuit board pads (19). An Independent claim is given for (A) a semiconductor memory (storage) device, (B) use of a circuit board device.
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公开(公告)号：DE10050761A1
公开(公告)日：2002-05-16
申请号：DE10050761
申请日：2000-10-13
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FEURLE ROBERT
IPC: G05F1/56
Abstract: The circuit has an input for an unregulated voltage, connected to a reference voltage generator (RG) and a series element (LE). The series element outputs a regulated voltage (UG). The series element includes two transistors (T1,T2) whose control inputs are connected to the input of the series element. The controlled section of at least one transistor (T2) can be separably coupled to the output of the series element.
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公开(公告)号：DE10115817B4
公开(公告)日：2008-02-28
申请号：DE10115817
申请日：2001-03-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： TAEUBER ANDREAS , DORTU JEAN-MARC , SCHMOELZ PAUL , FEURLE ROBERT
IPC: G11C11/407 , G11C7/10 , G11C11/4093
Abstract: The integrated memory chip has an external control terminal, a dynamic memory, and a control circuit for controlling a memory access to the dynamic memory. The control circuit is connected to the external control terminal, for receiving an access command indicating the beginning of a memory access. The control circuit further has an output, which is connected to the dynamic memory, for outputting at least one activation signal, read command or write command and precharge command generated from the access command. This makes it possible, in the case of use in a data processing system, to dispense with a DRAM controller provided outside the memory chip.
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公开(公告)号：DE10115816B4
公开(公告)日：2008-02-28
申请号：DE10115816
申请日：2001-03-30
Applicant: INFINEON TECHNOLOGIES AG
Inventor： TAEUBER ANDREAS , DORTU JEAN-MARC , SCHMOELZ PAUL , FEURLE ROBERT
IPC: G11C11/407 , G11C7/22 , G11C11/4076 , G11C11/408
Abstract: In order to operate an integrated dynamic memory having a memory cell array having bit lines and word lines a plurality of individual actions-to be performed for a memory access-from the activation of one of the word lines up to the precharging of the word lines are controlled in a synchronized manner with a clock signal. A value for defining a defined number of clock cycles between at least two individual actions is programmed at the beginning. For this purpose, a control circuit has a programmable unit. In this way, in conjunction with a clocked circuit, a comparatively high data throughput is made possible even at variable clock frequencies.
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公开(公告)号：DE19961518B4
公开(公告)日：2007-03-29
申请号：DE19961518
申请日：1999-12-20
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FEURLE ROBERT
Abstract: A method for operating a current sense amplifier having a latch configuration improves the signal-to-noise ratio by setting the supply voltage for the latch configuration to be greater than a voltage which is present at the input of the current sense amplifier.
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Patent Agency Ranking
公开(公告)号：DE10126115B4
公开(公告)日：2005-06-30
申请号：DE10126115
申请日：2001-05-29
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FEURLE ROBERT , DORTU JEAN-MARC , TAEUBER ANDREAS , SCHMOELZ PAUL
IPC: G11C7/10 , G11C11/407
Abstract: A data output interface, in particular for semiconductor memories, provides a plurality of output drivers for providing data output signals in a manner dependent on a read command and a clock signal. In order to signal to a microprocessor that can be connected to the data output that data are provided, a data provision signal is additionally provided by a further output driver. The arrangement described can preferably be used for DDR-SDRAMs and enables particularly high clock frequencies.
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公开(公告)号：DE50010202D1
公开(公告)日：2005-06-09
申请号：DE50010202
申请日：2000-02-07
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FEURLE ROBERT , SCHNEIDER HELMUT
IPC: H01L21/302 , H01L21/3065 , H01L21/768 , H01L23/522 , H01L23/528
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公开(公告)号：DE19946203B4
公开(公告)日：2004-05-06
申请号：DE19946203
申请日：1999-09-27
Applicant: INFINEON TECHNOLOGIES AG
Inventor： SCHNEIDER HELMUT , FEURLE ROBERT
IPC: H01L23/525 , H01L27/112
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公开(公告)号：DE10156749A1
公开(公告)日：2003-06-26
申请号：DE10156749
申请日：2001-11-19
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FEURLE ROBERT , DORTU JEAN-MARC , TAEUBER ANDREAS , SCHMOELZ PAUL
IPC: G11C7/10 , G06F12/00 , G11C11/408
Abstract: The memory device has a memory area (114) for storing data, an input (126) for receiving a data bundle comprising a number of time-sequential data blocks. A further input (112) receives a data mask signal associated with the data bundle. A device (112) receives one data block to be written into the memory area, independently of the data mask signal. A device writes the received data block into the memory area. Independent claims are also included for the following: (1) a processor system; and (2) a method of performing write operations into a memory area.
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公开(公告)号：DE10139085A1
公开(公告)日：2003-05-22
申请号：DE10139085
申请日：2001-08-16
Applicant: INFINEON TECHNOLOGIES AG
Inventor： FEURLE ROBERT
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