公开(公告)号：JP2000150564A

公开(公告)日：2000-05-30

申请号：JP31978699

申请日：1999-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: H01L21/60 ,  G01R31/28 ,  G01R31/3185 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To reduce various modes of a test program for testing a semiconductor chip and a time required for it by connecting all bonding pads to an external terminal, so that a bonding pad which is not used during normal operation is used only for exchanging an input data and an output data during test operation. SOLUTION: A semiconductor chip is provided with a bonding pad IOP for changing the organization mode of data input/data output, and all the bonding pads IOP are connected to an external terminal. A bonding option pad BOPi is wire-connected to an external electric potential as well as bonding option pads BOP1-5. At the test operation of a chip A, all bondings IOP0-7 for exchanging input data and output data are used. In short, a bonding pad IOP which is not used in the organization state of DQ4 in normal operation is used for test operation.

公开(公告)号：JP2002198442A

公开(公告)日：2002-07-12

申请号：JP2001340062

申请日：2001-11-05

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BROX MARTIN ,  KAISER ROBERT ,  PFEFFERL KARL-PETER ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: G11C11/401 ,  G11C5/02 ,  H01L21/8242 ,  H01L23/485 ,  H01L23/50 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a memory block having a flexible structure. SOLUTION: The memory structure has a contact block (1), and cell blocks (2-9) adjacent to the contact block (1). The contact block (1) is located in the center, the cell blocks (2-9) abut on the four sides of the contact block (1), respectively, and the cell blocks (2-9) are arranged annularly around the contact block (1). The cell block (2) has two sides abutting, respectively, on two other cell blocks (3, 9) and the cell blocks (2-9) are divided into first and second sub-cell blocks (21, 22) in the longitudinal direction.

公开(公告)号：JP2000243933A

公开(公告)日：2000-09-08

申请号：JP2000038344

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SCHNEIDER HELMUT

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a decoder connecting device for a memory chip having a long bit line. SOLUTION: A dummy region 7 of a decoder 2 based on a bit line twist 8 is provided between a current supply line 3 and a decoder 2. In this case, bit lines BL form a line twist in a bit line twist region 8 in a memory cell field 1. Additional through holes 6 between two metallized surfaces are made in a zone of the decoder region 2 adjacent to the bit line twist region 8.

公开(公告)号：JP2000286345A

公开(公告)日：2000-10-13

申请号：JP2000069416

申请日：2000-03-13

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHNEIDER HELMUT ,  LINDOLF JUERGEN ,  BORST THOMAS ,  RUCKERBAUER HERMANN

IPC: H01L21/761 ,  H01L21/8234 ,  H01L27/088 ,  H01L29/10 ,  H01L29/78 ,  H03F3/16

Abstract: PROBLEM TO BE SOLVED: To adjust and set the turn-on voltage to a specified value even when using a short channel transistor in a read amplifier by installing a field-effect transistor having a variable bus tab potential in a bus tab separated from the other elements in a semiconductor substrate. SOLUTION: On an n--type semiconductor substrate 4, a p-type epitaxial layer 5 is disposed. Between the semiconductor substrate 4 and the epitaxial layer 5, an n+-type buried layer 6 is formed. The n+-type buried layer 6 forms a bus tab 9 together with an n-type drain D and n-type diffusion regions 7, 8. The diffusion regions are disposed in the bus tab 9, separating a field-effect transistor 10 having the n-type drain D, the source S, and the gate G made of polycrystalline silicon from the other elements. The bus tab potential is supplied to the field-effect transistor 10 through a p+-type region having a connection terminal B to set the turn-on voltage to a specified value.

公开(公告)号：JP2000243925A

公开(公告)日：2000-09-08

申请号：JP2000038348

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  KAISER ROBERT ,  SCHNEIDER HELMUT

IPC: H01L27/10 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To supply power required for activating a memory cell field immediately with simple structure via a short power feed line by setting a first electrical connection line to a high ohmic state and a second electrical connection line to a low ohmic state. SOLUTION: A semiconductor integrated memory device consists of memory cell fields 1-8, and the cell fields 1-8 are arranged in a line and are interconnected via power feed lines 11 and 12 with low ohmic at both sides. Also, a power feed line 13 with low ohmic is connected to the surrounding of each of memory cell fields 1-8. Then, a sense amplifier 5 exists at regions among the memory cell fields 1-8. The power feed lines 11, 12, and 13 with low ohmic form a low-ohmic power supply circuit network, and the circuit network is connected to a power supply generator 9 via a high-ohmic line 10.

公开(公告)号：JP2001257568A

公开(公告)日：2001-09-21

申请号：JP2001031274

申请日：2001-02-07

Applicant: INFINEON TECHNOLOGIES AG

Inventor： KAISER ROBERT ,  KRASSER HANS-JURGEN ,  SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G01R31/3183 ,  G01R31/3185 ,  H03K5/13 ,  H03K5/131 ,  H03K5/133

Abstract: PROBLEM TO BE SOLVED: To provide a simply structured device capable of forming a signal pulse having a prescribed pulse length by a module itself by improving the device. SOLUTION: A variable delay element consists of the serial circuit of an inverter, and a signal section free from delay for writing to each register and a signal section free from delay for reading from the register are arranged in parallel in this inverter.

公开(公告)号：JP2000353749A

公开(公告)日：2000-12-19

申请号：JP2000133724

申请日：2000-05-02

Applicant: INFINEON TECHNOLOGIES AG

Inventor： SCHAMBERGER FLORIAN ,  SCHNEIDER HELMUT

IPC: H01L21/82 ,  G11C16/02 ,  G11C17/16 ,  H03K19/173

Abstract: PROBLEM TO BE SOLVED: To obtain a circuit device, which can supervise patterning process of an element capable of being electrically programmed in a programming process and is used for programming the electrically programmable element. SOLUTION: Resistance of a conductor path of an element, capable of being programmed in a circuit device has an element T1, which can be continuously changed by a current or a voltage and can be switched for programming the programmable element. Both of the elements are series-connected and are connected with a first feeder potential or a second feeder potential. A supervisory circuit 1 is series-connected with a series circuit, connecting the programmable element with the element T1 which is capable of being switched between a terminal for the first feeder potential and a terminal for the second feeder potential for making the measurement of the amount of electrical characteristics to characterize a programming process. Hereby, the operating process of an electrically programmable element can be supervised in the programming process.

公开(公告)号：JP2000252440A

公开(公告)日：2000-09-14

申请号：JP2000046287

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SAVIGNAC DOMINIQUE DR ,  SCHNEIDER HELMUT

IPC: G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid the affect of unevenness of the element at edge part on a crossover region or twist region of a bit line by providing with a bit line comprising no bit line twist part with a dummy contact communicated with another plane. SOLUTION: Bit lines BL1, BL2; BL5, BL6; BL9, BL10 comprise a bit line twist part. Bit lines BL3, BL4, BL7, and BL8 comprise no bit line twist part. In order to avoid a proximity effect caused by discontinuity or unevenness in a region near the word lines, even the bit lines BL3, BL4, BL7, and BL8 comprising no crossover or twist part are provided with dummy contacts 8-11. The dummy contacts 8-11 are connected to a word line plane from upward from a bit line plane, and terminate there. Thus, the effect of unevenness of word line is avoided.

公开(公告)号：JP2000252439A

公开(公告)日：2000-09-14

申请号：JP2000045945

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  G11C7/06 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid a critical diffusion region interval between sense amplifier transistor groups for optimum combination with a sense amplifier transistor by arranging a driver for the sense amplifier transistor parallel to a diffusion region while directly adjacent to it. SOLUTION: For a transistor 6 of each conductive type, one diffusion region 8 extending as band is provided, respectively. For the diffusion region 8 for the sense amplifier transistor 6, one driver 5 is provided parallel to it, respectively. Thus, a critical diffusion region interval is avoided at completion. An optimum combination between the driver 5 and the sense amplifier transistor 6 is possible, with no such large wiring resistance as to delay an electric-charge transfer. Thus, an optimum combination to the driver 5 of the sense amplifier transistor is performed with no large wiring resistance accompanied, allowing a perfect molten structure of the diffusion region 8 of the sense amplifier transistor 6.

公开(公告)号：JP2002063800A

公开(公告)日：2002-02-28

申请号：JP2001157851

申请日：2001-05-25

Applicant: INFINEON TECHNOLOGIES AG

Inventor： BRASS ECKHARD ,  SCHAFFROTH THILO ,  SCHNABEL JOACHIM ,  SCHNEIDER HELMUT

IPC: G01R31/28 ,  G11C11/401 ,  G11C29/12 ,  G11C29/26 ,  H01L27/10 ,  G11C29/00

Abstract: PROBLEM TO BE SOLVED: To provide a method for testing many word lines of a semiconductor memory assembly in a multiple WL wafer test in which a multiple wafer test can be performed quickly without needing much cost. SOLUTION: When an active word line(WL) is in a power-down state, a non-active word line is separated from negative VNWL voltage and made highly resistant immediately before the power-down of the active word line to prevent the rise of the non-active word line having negative voltage.