公开(公告)号：JP2000150564A

公开(公告)日：2000-05-30

申请号：JP31978699

申请日：1999-11-10

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: H01L21/60 ,  G01R31/28 ,  G01R31/3185 ,  G11C11/401

Abstract: PROBLEM TO BE SOLVED: To reduce various modes of a test program for testing a semiconductor chip and a time required for it by connecting all bonding pads to an external terminal, so that a bonding pad which is not used during normal operation is used only for exchanging an input data and an output data during test operation. SOLUTION: A semiconductor chip is provided with a bonding pad IOP for changing the organization mode of data input/data output, and all the bonding pads IOP are connected to an external terminal. A bonding option pad BOPi is wire-connected to an external electric potential as well as bonding option pads BOP1-5. At the test operation of a chip A, all bondings IOP0-7 for exchanging input data and output data are used. In short, a bonding pad IOP which is not used in the organization state of DQ4 in normal operation is used for test operation.

公开(公告)号：JP2000243925A

公开(公告)日：2000-09-08

申请号：JP2000038348

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  KAISER ROBERT ,  SCHNEIDER HELMUT

IPC: H01L27/10 ,  G11C5/02 ,  G11C5/14 ,  G11C7/00 ,  H01L23/528 ,  H01L27/02 ,  H01L27/105 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To supply power required for activating a memory cell field immediately with simple structure via a short power feed line by setting a first electrical connection line to a high ohmic state and a second electrical connection line to a low ohmic state. SOLUTION: A semiconductor integrated memory device consists of memory cell fields 1-8, and the cell fields 1-8 are arranged in a line and are interconnected via power feed lines 11 and 12 with low ohmic at both sides. Also, a power feed line 13 with low ohmic is connected to the surrounding of each of memory cell fields 1-8. Then, a sense amplifier 5 exists at regions among the memory cell fields 1-8. The power feed lines 11, 12, and 13 with low ohmic form a low-ohmic power supply circuit network, and the circuit network is connected to a power supply generator 9 via a high-ohmic line 10.

公开(公告)号：JP2000243933A

公开(公告)日：2000-09-08

申请号：JP2000038344

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SCHNEIDER HELMUT

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a decoder connecting device for a memory chip having a long bit line. SOLUTION: A dummy region 7 of a decoder 2 based on a bit line twist 8 is provided between a current supply line 3 and a decoder 2. In this case, bit lines BL form a line twist in a bit line twist region 8 in a memory cell field 1. Additional through holes 6 between two metallized surfaces are made in a zone of the decoder region 2 adjacent to the bit line twist region 8.

公开(公告)号：JP2000252440A

公开(公告)日：2000-09-14

申请号：JP2000046287

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SAVIGNAC DOMINIQUE DR ,  SCHNEIDER HELMUT

IPC: G11C7/18 ,  H01L21/8242 ,  H01L23/522 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid the affect of unevenness of the element at edge part on a crossover region or twist region of a bit line by providing with a bit line comprising no bit line twist part with a dummy contact communicated with another plane. SOLUTION: Bit lines BL1, BL2; BL5, BL6; BL9, BL10 comprise a bit line twist part. Bit lines BL3, BL4, BL7, and BL8 comprise no bit line twist part. In order to avoid a proximity effect caused by discontinuity or unevenness in a region near the word lines, even the bit lines BL3, BL4, BL7, and BL8 comprising no crossover or twist part are provided with dummy contacts 8-11. The dummy contacts 8-11 are connected to a word line plane from upward from a bit line plane, and terminate there. Thus, the effect of unevenness of word line is avoided.

公开(公告)号：JP2000252439A

公开(公告)日：2000-09-14

申请号：JP2000045945

申请日：2000-02-23

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  G11C7/06 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To avoid a critical diffusion region interval between sense amplifier transistor groups for optimum combination with a sense amplifier transistor by arranging a driver for the sense amplifier transistor parallel to a diffusion region while directly adjacent to it. SOLUTION: For a transistor 6 of each conductive type, one diffusion region 8 extending as band is provided, respectively. For the diffusion region 8 for the sense amplifier transistor 6, one driver 5 is provided parallel to it, respectively. Thus, a critical diffusion region interval is avoided at completion. An optimum combination between the driver 5 and the sense amplifier transistor 6 is possible, with no such large wiring resistance as to delay an electric-charge transfer. Thus, an optimum combination to the driver 5 of the sense amplifier transistor is performed with no large wiring resistance accompanied, allowing a perfect molten structure of the diffusion region 8 of the sense amplifier transistor 6.

公开(公告)号：JP2001203172A

公开(公告)日：2001-07-27

申请号：JP2000383537

申请日：2000-12-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SAVIGNAC DOMINIQUE DR

IPC: H01L21/301 ,  H01L23/31

Abstract: PROBLEM TO BE SOLVED: To enable simply avoiding cracks with high reliability when a semiconductor wafer is cut off, by improving equipment for cutting off semiconductor elements from a semiconductor wafer along a scribe line. SOLUTION: In this equipment for cutting off semiconductor elements, an insulating layer is formed on a semiconductor wafer, a plurality of metallization surfaces are formed on the insulating layer, and the uppermost metallization surface from among these metallization surfaces is connected electrically with the metallization surface below the uppermost metallization surface via a connection layer with a connection hole. An additional recessed part, which is formed together with the connection hole is formed on the insulating layer at an interim region between the semiconductor elements and the scribe line, so that the insulating layer is thinned.

公开(公告)号：JP2000252438A

公开(公告)日：2000-09-14

申请号：JP2000043268

申请日：2000-02-21

Applicant: INFINEON TECHNOLOGIES AG

Inventor： CHRYSOSTOMIDES ATHANASIA ,  FEURLE ROBERT ,  SAVIGNAC DOMINIQUE ,  SCHNEIDER HELMUT

IPC: H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor storage device wherein components are little affected by neighborhood action at manufacturing, providing connected diffusion regions. SOLUTION: Provided on a vacant surface 4, a dummy component 3 is identical with a component adjacent to a memory cell field or similar, as possible, to the component, while provided in the connected diffusion regions 5 common to the component adjacent to the dummy component.

公开(公告)号：JP2000243837A

公开(公告)日：2000-09-08

申请号：JP2000038349

申请日：2000-02-16

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  SCHNEIDER HELMUT

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

Abstract: PROBLEM TO BE SOLVED: To make it possible to reliably avoid the instability at each critical spot on conductor paths by a method wherein the conductor paths are supported by dummy contacts at the critical spots due to a layout. SOLUTION: The conductor paths 10 and 11 and 14 and 15 out of conductor paths 10 to 15 are respectively crossovered mutually at twisted regions. When the conductor paths 10 to 15 are metallized, critical spots are respectively generated at places, where a discontinuity is generated for a proximity effect in the proximity parts of the conductor paths, on the conductor paths. Such the discontinuity is generated in the case where one of the conductor paths adjacent to each other is blockaded. At this uncontinuous place, the conductor path has an instability and a breaking of the conductor path is caused. Dummy contacts 16 to 20 are respectively provided on these critical spots and these dummy contacts 16 to 20 lead to the plane positioned under the lower part of the plane of the conductor paths. Thereby, the instability of the conductor paths or the breaking of the conductor paths can be reliably avoided.

公开(公告)号：DE50009385D1

公开(公告)日：2005-03-10

申请号：DE50009385

申请日：2000-02-18

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT ,  MANDEL SABINE ,  SCHNEIDER HELMUT

IPC: G11C8/00 ,  G11C5/02 ,  G11C5/14 ,  G11C7/18 ,  H01L21/8242 ,  H01L27/108

Abstract: A decoder connection configuration for memory chips, in which, in a dummy region of a decoder, the dummy region being caused by a bit line twist, additional plated-through holes are provided between power supply lines and the decoder. By virtue of the bit line twist, the coupling capacitance is practically halved on account of the electrical symmetry.

公开(公告)号：DE10102350B4

公开(公告)日：2004-09-23

申请号：DE10102350

申请日：2001-01-19

Applicant: INFINEON TECHNOLOGIES AG

Inventor： FEURLE ROBERT

IPC: G11C7/10 ,  G11C11/407

Abstract: An integrated memory has a plurality of memory cell arrays. The memory cell arrays are in each case assigned a decoder for selecting bit lines and word lines. In order to trigger an access cycle for a memory cell access, a write command or a read command with an active state is generated. Within the access cycle, under the control of a control circuit, respective decoders of the memory cell arrays are driven and data of each of the memory cell arrays are successively read out or written in for as long as the read command or write command remains in the active state. As a result, it is possible to set a comparatively large variable burst length of the memory. A method for operating an integrated memory is also provided.