公开(公告)号：US20190355725A1

公开(公告)日：2019-11-21

申请号：US16461697

申请日：2016-12-28

Applicant: Intel Corporation

Inventor： Van Le ,  Abhishek Sharma ,  Gilbert Dewey ,  Ravi Pillarisetty ,  Shriram Shivaraman ,  Tahir Ghani ,  Jack Kavalieros

IPC: H01L27/108 ,  H01L29/22 ,  H01L29/66 ,  H01L29/786 ,  H01L29/423

Abstract: Non-planar thin film transistors (TFTs) incorporating an oxide semiconductor for the channel material. Memory devices may include an array of one thin film transistor and one capacitor (1TFT-1C) memory cells. Methods for fabricating non-planar thin film transistors may include a sacrificial gate/top-gate replacement technique with self-alignment of source/drain contacts.

公开(公告)号：US20190043560A1

公开(公告)日：2019-02-07

申请号：US16146473

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Huseyin Ekin Sumbul ,  Gregory K. Chen ,  Raghavan Kumar ,  Phil Knag ,  Abhishek Sharma ,  Sasikanth Manipatruni ,  Amrita Mathuriya ,  Ram Krishnamurthy ,  Ian A. Young

IPC: G11C11/418 ,  G06F7/544 ,  G06F9/30 ,  G11C13/00 ,  G11C11/419

Abstract: A memory circuit has compute-in-memory circuitry that enables a multiply-accumulate (MAC) operation based on shared charge. Row access circuitry drives multiple rows of a memory array to multiply a first data word with a second data word stored in the memory array. The row access circuitry drives the multiple rows based on the bit pattern of the first data word. Column access circuitry drives a column of the memory array when the rows are driven. Accessed rows discharge the column line in an accumulative fashion. Sensing circuitry can sense voltage on the column line. A processor in the memory circuit computes a MAC value based on the voltage sensed on the column.

公开(公告)号：US12142689B2

公开(公告)日：2024-11-12

申请号：US17940949

申请日：2022-09-08

Applicant: Intel Corporation

Inventor： Sean Ma ,  Abhishek Sharma ,  Gilbert Dewey ,  Jack T. Kavalieros ,  Van H. Le

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/417 ,  H01L29/49 ,  H01L29/78

Abstract: A transistor is described. The transistor includes a substrate, a first semiconductor structure above the substrate, a second semiconductor structure above the substrate, a source contact that includes a first metal structure that contacts a plurality of surfaces of the first semiconductor structure and a drain contact that includes a second metal structure that contacts a plurality of surfaces of the second semiconductor structure. The transistor also includes a gate below a back side of the substrate.

公开(公告)号：US12107170B2

公开(公告)日：2024-10-01

申请号：US17517583

申请日：2021-11-02

Applicant: Intel Corporation

Inventor： Carl Naylor ,  Abhishek Sharma ,  Mauro Kobrinsky ,  Christopher Jezewski ,  Urusa Alaan ,  Justin Weber

IPC: H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/78609 ,  H01L27/1207 ,  H01L29/66969 ,  H01L29/7869

Abstract: Transistor structures with a channel semiconductor material that is passivated with two-dimensional (2D) crystalline material. The 2D material may comprise a semiconductor having a bandgap offset from a band of the channel semiconductor. The 2D material may be a thin as a few monolayers and have good temperature stability. The 2D material may be a conversion product of a sacrificial precursor material, or of a portion of the channel semiconductor material. The 2D material may comprise one or more metal and a chalcogen. The channel material may be a metal oxide semiconductor suitable for low temperature processing (e.g., IGZO), and the 2D material may also be compatible with low temperature processing (e.g.,

公开(公告)号：US11881517B2

公开(公告)日：2024-01-23

申请号：US17724331

申请日：2022-04-19

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Cory Weber ,  Van H. Le ,  Sean Ma

IPC: H01L29/47 ,  H01L29/66 ,  H01L29/45 ,  H01L29/786 ,  H01L29/423 ,  H10B12/00 ,  H10B63/00

CPC classification number: H01L29/47 ,  H01L29/42356 ,  H01L29/66742 ,  H01L29/786 ,  H10B12/30 ,  H10B63/30

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a gate electrode above the substrate, and a channel layer above the substrate, separated from the gate electrode by a gate dielectric layer. The transistor further includes a contact electrode above the channel layer and in contact with a contact area of the channel layer. The contact area has a thickness determined based on a Schottky barrier height of a Schottky barrier formed at an interface between the contact electrode and the contact area, a doping concentration of the contact area, and a contact resistance at the interface between the contact electrode and the contact area. Other embodiments may be described and/or claimed.

公开(公告)号：US20240006415A1

公开(公告)日：2024-01-04

申请号：US17856885

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Abhishek Sharma ,  Wilfred Gomes ,  Tahir Ghani ,  Anand Murthy

IPC: H01L27/092 ,  H01L23/473 ,  H01L23/528 ,  H01L29/06 ,  H01L29/08 ,  H01L29/423 ,  H01L29/417 ,  H01L29/786 ,  H01L29/775 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0922 ,  H01L23/473 ,  H01L23/5286 ,  H01L29/0673 ,  H01L29/0847 ,  H01L29/42392 ,  H01L29/41733 ,  H01L29/78696 ,  H01L29/775 ,  H01L21/02603 ,  H01L21/8221 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823871 ,  H01L29/66742 ,  H01L29/66439

Abstract: Techniques and mechanisms for providing an integrated circuit (IC) which comprises an interconnect that extends between channel structures of two transistors. In an embodiment, a separation layer is provided between a first stack of channel structures and a second stack of channel structures, wherein an interior region of the separation layer comprises a sacrificial material which spans on overlap region between the stacks. Fabrication processes form a hole which exposes the interior region, and etching is performed to remove the sacrificial material from the separation layer. Subsequently, deposition processing forms in the interior region a trace portion of the interconnect. In another embodiment, the interconnect comprises a contiguous body of a conductor material, wherein the contiguous body extends to form respective regions of the trace portion, and a via portion of the interconnect.

公开(公告)号：US11862729B2

公开(公告)日：2024-01-02

申请号：US17584260

申请日：2022-01-25

Applicant: Intel Corporation

Inventor： Yih Wang ,  Abhishek Sharma ,  Sean Ma ,  Van H. Le

IPC: H01L29/786 ,  H01L29/66 ,  H10B12/00

CPC classification number: H01L29/78642 ,  H01L29/66742 ,  H10B12/053 ,  H10B12/34 ,  H10B12/488

Abstract: Vertical thin film transistors (TFTs) including a gate electrode pillar clad with a gate dielectric. The gate dielectric is further clad with a semiconductor layer. Source or drain metallization is embedded in trenches formed in an isolation dielectric adjacent to separate regions of the semiconductor layer. During TFT operation, biasing of the gate electrode can induce one or more transistor channel within the semiconductor layer, electrically coupling together the source and drain metallization. A width of the channel may be proportional to a height of the gate electrode pillar clad by the semiconductor layer, while a length of the channel may be proportional to the spacing between contacts occupied by the semiconductor layer. In some embodiments, a memory device may include cells comprising a vertical thin film select transistor and a capacitor (1TFT-1C).

公开(公告)号：US11616057B2

公开(公告)日：2023-03-28

申请号：US16367144

申请日：2019-03-27

Applicant: Intel Corporation

Inventor： Prashant Majhi ,  Abhishek Sharma ,  Brian Doyle ,  Ravi Pillarisetty ,  Willy Rachmady

IPC: H01L27/06 ,  H01L23/528 ,  H01L21/02 ,  H01L29/267

Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

公开(公告)号：US11437405B2

公开(公告)日：2022-09-06

申请号：US16024696

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Patrick Morrow ,  Aaron Lilak ,  Willy Rachmady ,  Anh Phan ,  Ehren Mannebach ,  Hui Jae Yoo ,  Abhishek Sharma ,  Van H. Le ,  Cheng-Ying Huang

IPC: H01L29/78 ,  H01L27/12 ,  H01L21/82 ,  H01L29/786 ,  H01L21/8258

Abstract: Embodiments herein describe techniques for an integrated circuit (IC). The IC may include a first transistor, an insulator layer above the first transistor, and a second transistor above the insulator layer. The first transistor may be a p-type transistor including a channel in a substrate, a first source electrode, and a first drain electrode. A first metal contact may be coupled to the first source electrode, while a second metal contact may be coupled to the first drain electrode. The insulator layer may be next to the first metal contact, and next to the second metal contact. The second transistor may include a second source electrode, and a second drain electrode. The second source electrode may be coupled to the first metal contact, or the second drain electrode may be coupled to the second metal contact. Other embodiments may be described and/or claimed.

公开(公告)号：US20220197829A1

公开(公告)日：2022-06-23

申请号：US17128804

申请日：2020-12-21

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Martin Dixon ,  Abhishek Sharma

IPC: G06F12/14 ,  G06F12/06 ,  G06F12/02 ,  G06F12/1009 ,  G06F12/0882

Abstract: An embodiment of an apparatus may include a processor, memory communicatively coupled to the processor, and circuitry communicatively coupled to the processor and the memory, the circuitry to manage a portion of the memory as hidden memory outside a range of physical memory accessible by user applications, and control access to the hidden memory from the processor with hidden page tables. Other embodiments are disclosed and claimed.