公开(公告)号：US11171207B2

公开(公告)日：2021-11-09

申请号：US16647695

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/205 ,  H01L29/423 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20210202319A1

公开(公告)日：2021-07-01

申请号：US16728903

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Ashish Agrawal ,  Gilbert Dewey ,  Cheng-Ying Huang ,  Willy Rachmady ,  Anand Murthy ,  Ryan Keech ,  Cory Bomberger

IPC: H01L21/822 ,  H01L27/12 ,  H01L29/08 ,  H01L23/522 ,  H01L29/417 ,  H01L21/8238

Abstract: A monolithic three-dimensional integrated circuit may include multiple transistor levels separated by one or more levels of metallization. An upper level transistor structure may include monocrystalline source and drain material epitaxially grown from a monocrystalline channel material at a temperature low enough to avoid degradation of a lower level transistor structure and/or degradation of one or more low-k dielectric materials between the transistor levels. A highly conductive n-type silicon source and drain material may be selectively deposited at low temperatures with a high pressure CVD process. Multiple crystals of source drain material arranged in a vertically stacked multi-channel transistor structure may be contacted by a single contact metallization.

公开(公告)号：US20200295003A1

公开(公告)日：2020-09-17

申请号：US16354960

申请日：2019-03-15

Applicant: INTEL CORPORATION

Inventor： Gilbert W. Dewey ,  Jack T. Kavalieros ,  Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Kimin Jun ,  Patrick Morrow ,  Aaron D. Lilak ,  Ehren Mannebach ,  Anh Phan

IPC: H01L27/092 ,  H01L29/16 ,  H01L29/20 ,  H01L29/06 ,  H01L29/78 ,  H01L21/8238 ,  H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L23/538 ,  H01L29/10

Abstract: Disclosed herein are stacked transistors having device strata with different channel widths, as well as related methods and devices. In some embodiments, an integrated circuit structure may include stacked strata of transistors, wherein different channel materials of different strata have different widths.

公开(公告)号：US20200279916A1

公开(公告)日：2020-09-03

申请号：US16647695

申请日：2017-12-20

Applicant: INTEL CORPORATION

Inventor： Willy Rachmady ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Nicholas G. Minutillo ,  Sean T. Ma ,  Anand S. Murthy ,  Jack T. Kavalieros ,  Tahir Ghani ,  Gilbert Dewey

IPC: H01L29/06 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/78 ,  H01L29/205 ,  H01L29/66

Abstract: A transistor includes a body of semiconductor material with a gate structure in contact with a portion of the body. A source region contacts the body adjacent the gate structure and a drain region contacts the body adjacent the gate structure such that the portion of the body is between the source region and the drain region. A first isolation region is under the source region and has a top surface in contact with a bottom surface of the source region. A second isolation region is under the drain region and has a top surface in contact with a bottom surface of the drain region. Depending on the transistor configuration, a major portion of the inner-facing sidewalls of the first and second isolation regions contact respective sidewalls of either a subfin structure (e.g., FinFET transistor configurations) or a lower portion of a gate structure (e.g., gate-all-around transistor configuration).

公开(公告)号：US20200168724A1

公开(公告)日：2020-05-28

申请号：US16632266

申请日：2017-08-18

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Willy Rachmady ,  Matthew V. Metz ,  Ashish Agrawal ,  Benjamin Chu-Kung ,  Uygar E. Avci ,  Jack T. Kavalieros ,  Ian A. Young

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78

Abstract: Disclosed herein are tunneling field effect transistors (TFETs), and related methods and computing devices. In some embodiments, a TFET may include: a first source/drain material having a p-type conductivity; a second source/drain material having an n-type conductivity; a channel material at least partially between the first source/drain material and the second source/drain material, wherein the channel material has a first side face and a second side face opposite the first side face; and a gate above the channel material, on the first side face, and on the second side face.

公开(公告)号：US20190172911A1

公开(公告)日：2019-06-06

申请号：US16325449

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Matthew V. Metz ,  Willy Rachmady ,  Gilbert Dewey ,  Jack T. Kavalieros

IPC: H01L29/15 ,  H01L29/423 ,  H01L29/78 ,  H01L21/02

Abstract: An embodiment includes an apparatus comprising: a trench included in an insulation layer that is formed on a substrate, the trench having a top portion and a bottom portion between the top portion and the substrate; a first layer which comprises a first material and is included in the bottom portion; and a superlattice, in the trench and on the first layer, including second and third layers that directly contact each other; wherein: (a) the second and third layers respectively include second and third materials, (b) the second and third materials have different chemical compositions from each other, and (c) the first layer is thicker than each of the second and third. Other embodiments are described herein.

公开(公告)号：US12255137B2

公开(公告)日：2025-03-18

申请号：US18419015

申请日：2024-01-22

Applicant: Intel Corporation

Inventor： Ehren Mannebach ,  Aaron Lilak ,  Hui Jae Yoo ,  Patrick Morrow ,  Anh Phan ,  Willy Rachmady ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Rishabh Mehandru

IPC: H01L23/522 ,  H01L21/8234 ,  H01L25/16 ,  H01L29/06

Abstract: Embodiments disclosed herein include electronic systems with vias that include a horizontal and vertical portion in order to provide interconnects to stacked components, and methods of forming such systems. In an embodiment, an electronic system comprises a board, a package substrate electrically coupled to the board, and a die electrically coupled to the package substrate. In an embodiment the die comprises a stack of components, and a via adjacent to the stack of components, wherein the via comprises a vertical portion and a horizontal portion.

公开(公告)号：US12120865B2

公开(公告)日：2024-10-15

申请号：US17132981

申请日：2020-12-23

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ashish Agrawal ,  Gilbert Dewey ,  Abhishek A. Sharma ,  Wilfred Gomes ,  Jack Kavalieros

IPC: H10B12/00 ,  H01L21/683 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786 ,  H10B53/30

CPC classification number: H10B12/30 ,  H01L21/6835 ,  H01L29/0673 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78618 ,  H01L29/78696 ,  H10B12/03 ,  H10B12/05 ,  H10B53/30 ,  H01L2221/68363

Abstract: Monolithic two-dimensional (2D) arrays of double-sided DRAM cells including a frontside bit cell over a backside bit cell. Each double-sided cell includes a stacked transistor structure having at least a first transistor over a second transistor. Each double-sided cell further includes a first capacitor on a frontside of the stacked transistor structure and electrically coupled to a source/drain of the first transistor. Each double-sided cell further includes a second capacitor on a backside of the stacked transistor structure and electrically coupled to a source/drain of the second transistor. Frontside cell addressing interconnects are electrically coupled to other terminals of at least the first transistor while one or more backside addressing interconnects are electrically coupled to at least one terminal of the second transistor or second capacitor.

公开(公告)号：US20240170581A1

公开(公告)日：2024-05-23

申请号：US17992057

申请日：2022-11-22

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Ayan Kar ,  Patrick Morrow ,  Charles C. Kuo ,  Nicholas A. Thomson ,  Benjamin Orr ,  Kalyan C. Kolluru ,  Marko Radosavljevic ,  Jack T. Kavalieros

IPC: H01L29/861 ,  H01L27/02 ,  H01L27/06 ,  H01L29/06

CPC classification number: H01L29/8611 ,  H01L27/0255 ,  H01L27/0629 ,  H01L29/0649

Abstract: An integrated circuit structure includes a sub-fin having at least a first portion that is doped with a first type of dopant, and a second portion that is doped with a second type of dopant. A PN junction is between the first and second portions of the sub-fin. The first type of dopant is one of a p-type or an n-type dopant, and the second type of dopant is the other of the p-type or the n-type dopant. A first contact and a second contact comprise conductive material. In an example, the first contact and the second contact are respectively in contact with the first portion and the second portion of the sub-fin. A diode is formed based on the PN junction between the first and second portions, where the first contact is an anode contact of the diode, and the second contact is a cathode contact of the diode.

公开(公告)号：US11929435B2

公开(公告)日：2024-03-12

申请号：US17899429

申请日：2022-08-30

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani

IPC: H01L29/78 ,  H01L21/28 ,  H01L29/20 ,  H01L29/423 ,  H01L29/51 ,  H01L29/66

CPC classification number: H01L29/78391 ,  H01L29/2003 ,  H01L29/40111 ,  H01L29/42364 ,  H01L29/513 ,  H01L29/516 ,  H01L29/66522 ,  H01L29/6684

Abstract: Techniques are disclosed for an integrated circuit including a ferroelectric gate stack including a ferroelectric layer, an interfacial oxide layer, and a gate electrode. The ferroelectric layer can be voltage activated to switch between two ferroelectric states. Employing such a ferroelectric layer provides a reduction in leakage current in an off-state and provides an increase in charge in an on-state. The interfacial oxide layer can be formed between the ferroelectric layer and the gate electrode. Alternatively, the ferroelectric layer can be formed between the interfacial oxide layer and the gate electrode.