公开(公告)号：US11121940B2

公开(公告)日：2021-09-14

申请号：US15470664

申请日：2017-03-27

Applicant: Intel Corporation

Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Andrew Herdrich ,  Edwin Verplanke

IPC: H04L12/851 ,  H04L12/701 ,  H04L12/911 ,  H04L12/24 ,  H04L12/947 ,  H04L5/00

Abstract: Examples include techniques to meet quality of service (QoS) requirements for a fabric point to point connection. Examples include an application hosted by a compute node coupled with a fabric requesting bandwidth for a point to point connection through the fabric and the request being granted or not granted based at least partially on whether bandwidth is available for allocation to meet one or more QoS requirements.

公开(公告)号：US20210272467A1

公开(公告)日：2021-09-02

申请号：US17256105

申请日：2018-09-28

Applicant: Intel Corporation

Inventor： Shao-Wen Yang ,  Addicam V. Sanjay ,  Karthik Veeramani ,  Gabriel L. Silva ,  Marcos P. Da Silva ,  Jose A. Avalos ,  Stephen T. Palermo ,  Glen J. Anderson ,  Meng Shi ,  Benjamin W. Bair ,  Pete A. Denman ,  Reese L. Bowes ,  Rebecca A. Chierichetti ,  Ankur Agrawal ,  Mrutunjayya Mrutunjayya ,  Gerald A. Rogers ,  Shih-Wei Roger Chien ,  Lenitra M. Durham ,  Giuseppe Raffa ,  Irene Liew ,  Edwin Verplanke

IPC: G09B5/06 ,  G06T19/00 ,  G06F9/38 ,  G06F9/455

Abstract: In one embodiment, an apparatus comprises a memory and a processor. The memory is to store sensor data, wherein the sensor data is captured by a plurality of sensors within an educational environment. The processor is to: access the sensor data captured by the plurality of sensors; identify a student within the educational environment based on the sensor data; detect a plurality of events associated with the student based on the sensor data, wherein each event is indicative of an attention level of the student within the educational environment; generate a report based on the plurality of events associated with the student; and send the report to a third party associated with the student.

公开(公告)号：US10936490B2

公开(公告)日：2021-03-02

申请号：US15634785

申请日：2017-06-27

Applicant: Intel Corporation

Inventor： Andrew J. Herdrich ,  Edwin Verplanke ,  Stephen R. Van Doren ,  Ravishankar Iyer ,  Eric R. Wehage ,  Rupin H. Vakharwala ,  Rajesh M. Sankaran ,  Jeffrey D. Chamberlain ,  Julius Mandelblat ,  Yen-Cheng Liu ,  Stephen T. Palermo ,  Tsung-Yuan C. Tai

IPC: G06F12/08 ,  G06F12/0811 ,  G06F13/42 ,  G06F9/455 ,  G06F9/50 ,  G06F12/1009 ,  G06F13/16

Abstract: Method and apparatus for per-agent control and quality of service of shared resources in a chip multiprocessor platform is described herein. One embodiment of a system includes: a plurality of core and non-core requestors of shared resources, the shared resources to be provided by one or more resource providers, each of the plurality of core and non-core requestors to be associated with a resource-monitoring tag and a resource-control tag; a mapping table to store the resource monitoring and control tags associated with each non-core requestor; and a tagging circuitry to receive a resource request sent from a non-core requestor to a resource provider, the tagging circuitry to responsively modify the resource request to include the resource-monitoring and resource-control tags associated with the non-core requestor in accordance to the mapping table and send the modified resource request to the resource provider.

公开(公告)号：US10929323B2

公开(公告)日：2021-02-23

申请号：US16601137

申请日：2019-10-14

Applicant: Intel Corporation

Inventor： Ren Wang ,  Yipeng Wang ,  Andrew Herdrich ,  Jr-Shian Tsai ,  Tsung-Yuan C. Tai ,  Niall D. McDonnell ,  Hugh Wilkinson ,  Bradley A. Burres ,  Bruce Richardson ,  Namakkal N. Venkatesan ,  Debra Bernstein ,  Edwin Verplanke ,  Stephen R. Van Doren ,  An Yan ,  Andrew Cunningham ,  David Sonnier ,  Gage Eads ,  James T. Clee ,  Jamison D. Whitesell ,  Jerry Pirog ,  Jonathan Kenny ,  Joseph R. Hasting ,  Narender Vangati ,  Stephen Miller ,  Te K. Ma ,  William Burroughs

IPC: G06F13/37 ,  G06F9/54 ,  G06F12/0868 ,  G06F12/0811 ,  G06F13/16 ,  G06F12/04 ,  G06F9/38

Abstract: Apparatus and methods implementing a hardware queue management device for reducing inter-core data transfer overhead by offloading request management and data coherency tasks from the CPU cores. The apparatus include multi-core processors, a shared L3 or last-level cache (“LLC”), and a hardware queue management device to receive, store, and process inter-core data transfer requests. The hardware queue management device further comprises a resource management system to control the rate in which the cores may submit requests to reduce core stalls and dropped requests. Additionally, software instructions are introduced to optimize communication between the cores and the queue management device.

公开(公告)号：US20190229990A1

公开(公告)日：2019-07-25

申请号：US16370985

申请日：2019-03-30

Applicant: Intel Corporation

Inventor： Rashmin Patel ,  Monica Kenguva ,  Francesc Guim Bernat ,  Edwin Verplanke ,  Andrew J. Herdrich

IPC: H04L12/24

Abstract: Technologies for analyzing and optimizing workloads (e.g., virtual network functions) executing on edge resources are disclosed. According to one embodiment disclosed herein, a compute device launches a virtualized system including a virtual network function and a performance manager, the performance manager to monitor a current resource usage of the virtual network function as a function of a performance profile. The compute device determines, in response to a determination that one or more quality-of-service (QoS) requirements is not satisfied, whether one or more resources from the platform are available for satisfying the QoS requirements. The compute device receives, in response to a determination that the one or more resources are available for satisfying the QoS requirements, the one or more resources and updates the performance profile as a function of the received resources.

公开(公告)号：US20190104178A1

公开(公告)日：2019-04-04

申请号：US15721867

申请日：2017-09-30

Applicant: Intel Corporation

Inventor： Vadim Sukhomlinov ,  Kshitij A. Doshi ,  Edwin Verplanke

IPC: H04L29/08

Abstract: Disclosed embodiments relate to cloud scaling with non-blocking, non-spinning cross-domain event synchronization and data communication. In an example, a processor includes a memory to store multiple virtual hardware thread (VHTR) descriptors, each including an architectural state, a monitored address range, a priority, and an execution state, fetch circuitry to fetch instructions associated with a plurality of the multiple VNFs, decode circuitry to decode the fetched instructions, scheduling circuitry to allocate and pin a VHTR to each of the plurality of VNFs, schedule execution of a VHTR on each of a plurality of cores, set the execution state of the scheduled VHTR; and in response to a monitor instruction received from a given VHTR, pause the given VHTR and switch in another VHTR to use the core previously used by the given VHTR, and, upon detecting a store to the monitored address range, trigger execution of the given VHTR.

公开(公告)号：US20170180325A1

公开(公告)日：2017-06-22

申请号：US14979134

申请日：2015-12-22

Applicant: Intel Corporation

Inventor： Stephen T. Palermo ,  Hari K. Tadepalli ,  Rashmin N. Patel ,  Andrew J. Herdrich ,  Edwin Verplanke

IPC: H04L29/06 ,  H04L12/24

CPC classification number: H04L63/04 ,  G06F21/53 ,  G06F2221/2141 ,  H04L41/0806 ,  H04L41/0893 ,  H04L43/0847 ,  H04L63/102

Abstract: Technologies for enforcing virtual machine network access control include a network computing device that includes a plurality of virtual machines. The network computing device is configured to receive an access request from a virtual function assigned to a requesting virtual machine of the network computing device. The network computing device is additionally configured to determine a first privilege level assigned to the requesting machine and a second privilege level assigned to the destination virtual machine, and determine whether the requesting virtual machine is authorized to access the destination virtual machine based on a comparison of the first and second privilege levels. Upon determining the requesting virtual machine is authorized to access the destination virtual machine, the network computing device is additionally configured to allow the requesting virtual machine access to the destination virtual machine. Other embodiments are described herein.

公开(公告)号：US09454497B2

公开(公告)日：2016-09-27

申请号：US14460530

申请日：2014-08-15

Applicant: Intel Corporation

Inventor： Jun Nakajima ,  Jr-Shian Tsai ,  Ravi L. Sahita ,  Mesut A. Ergin ,  Edwin Verplanke ,  Rashmin N. Patel ,  Alexander W. Min ,  Ren Wang ,  Tsung-Yuan C. Tai

IPC: G06F12/14 ,  G06F9/455 ,  G06F21/44 ,  G06F21/60 ,  G06F9/50 ,  H04L12/931

CPC classification number: G06F12/1475 ,  G06F9/455 ,  G06F9/45558 ,  G06F9/50 ,  G06F21/44 ,  G06F21/606 ,  G06F2009/45583 ,  G06F2009/45587 ,  G06F2212/1052 ,  H04L49/70

Abstract: Technologies for secure inter-virtual-machine shared memory communication include a computing device with hardware virtualization support. A virtual machine monitor (VMM) authenticates a view switch component of a target virtual machine. The VMM adds configures a secure memory view to access a shared memory segment. The shared memory segment may include memory pages of a source virtual machine or the VMM. The view switch component switches to the secure memory view without generating a virtual machine exit event, using the hardware virtualization support. The view switch component may switch to the secure memory view by modifying an extended page table (EPT) pointer. The target virtual machine accesses the shared memory segment via the secure memory view. The target virtual machine and the source virtual machine may coordinate ownership of memory pages using a secure view control structure stored in the shared memory segment. Other embodiments are described and claimed.

Abstract translation: 用于安全的虚拟机间共享存储器通信的技术包括具有硬件虚拟化支持的计算设备。 虚拟机监视器（VMM）验证目标虚拟机的视图切换组件。 VMM添加配置安全内存视图以访问共享内存段。 共享内存段可以包括源虚拟机或VMM的存储器页面。 视图切换组件切换到安全存储器视图，而不会使用硬件虚拟化支持生成虚拟机退出事件。 视图切换组件可以通过修改扩展页表（EPT）指针来切换到安全存储器视图。 目标虚拟机通过安全内存视图访问共享内存段。 目标虚拟机和源虚拟机可以使用存储在共享存储器段中的安全视图控制结构来协调存储器页的所有权。 描述和要求保护其他实施例。