公开(公告)号：US20180286101A1

公开(公告)日：2018-10-04

申请号：US15476984

申请日：2017-04-01

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Paul S. Diefenbaugh ,  Atsuo Kuwahara

IPC: G06T15/00 ,  G06T1/60 ,  G06T1/20 ,  G06F1/32 ,  G09G5/36

CPC classification number: G06T15/005 ,  G06F1/3265 ,  G06T1/20 ,  G06T1/60 ,  G06T2210/52 ,  G09G5/363 ,  H04N19/17 ,  H04N19/42

Abstract: An embodiment of a graphics apparatus may include a frame divider to divide a frame into two or more sub-frames, and a parallelized post-render stage communicatively coupled to the frame divider to process a sub-frame of the two or more sub-frames in parallel with a render operation. The parallelized post-render stage may include a post-processor communicatively coupled to the frame divider to post-process a rendered sub-frame in parallel with the render operation. Other embodiments are disclosed and claimed.

公开(公告)号：US20180176565A1

公开(公告)日：2018-06-21

申请号：US15387186

申请日：2016-12-21

Applicant: INTEL CORPORATION

Inventor： Jason Tanner

IPC: H04N19/124 ,  H04N19/176 ,  H04N19/147 ,  H04N19/139

CPC classification number: H04N19/139 ,  H04N19/119 ,  H04N19/129 ,  H04N19/147 ,  H04N19/154 ,  H04N19/176

Abstract: A method for flexible encoding is described herein. The method includes selecting a largest coding unit size of a current frame based on a largest coding unit size of a prior frame and determining a coding unit processing order based on heuristics and the largest coding unit size of the current frame. The method also includes determining a rate distortion metric of the current frame based on the largest coding unit size and in response to an exit criteria being met, processing the coding units of the current frame in the coding unit processing order.

公开(公告)号：US20180007371A1

公开(公告)日：2018-01-04

申请号：US15200420

申请日：2016-07-01

Applicant: Intel Corporation

Inventor： Paul S. Diefenbaugh ,  Jason Tanner ,  Kristoffer D. Fleming ,  Vishal R. Sinha ,  Karthik Veeramani

IPC: H04N19/186 ,  H04N19/137 ,  H04N19/15 ,  H04N19/172

CPC classification number: H04N9/64 ,  G09G2320/0242 ,  H04N9/646 ,  H04N21/4122 ,  H04N21/4363 ,  H04N21/440227

Abstract: Sink devices are provided that increase quality of displayed images by dynamically integrating higher fidelity update frames into a base stream encoded using an encoding technique (e.g., chroma-subsampling and/or another lossless encoding technique). Use of base image frames enables backward compatibility with existing technology and serves as a baseline for bandwidth scaling. The fidelity update frames may include raw image data, lossy, or losslessly compressed image data, and/or additional subsampled image data. The image data included in the fidelity update frames may apply to the entire base image frame or a portion thereof. The fidelity update frames may include incremental data or complete, high fidelity image data for a portion of an entire image. The sink devices may store and implement fidelity management policies that control operation of the devices to balance resource consumption against fidelity to meet the needs of specific operational environments.

公开(公告)号：US11930159B2

公开(公告)日：2024-03-12

申请号：US16699243

申请日：2019-11-29

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Zhijun Lei

IPC: H04N19/105 ,  H04N19/119 ,  H04N19/142 ,  H04N19/176 ,  H04N19/426

CPC classification number: H04N19/105 ,  H04N19/119 ,  H04N19/142 ,  H04N19/176 ,  H04N19/427

Abstract: Methods, articles, and systems of video coding use intra block copying with hash-based searches.

公开(公告)号：US11924435B2

公开(公告)日：2024-03-05

申请号：US16875756

申请日：2020-05-15

Applicant: INTEL CORPORATION

Inventor： Srinivasan Embar Raghukrishnan ,  Jason Tanner ,  Naiqian Lu

IPC: H04N19/139 ,  H04N19/103 ,  H04N19/119 ,  H04N19/184 ,  H04N19/436

CPC classification number: H04N19/139 ,  H04N19/103 ,  H04N19/119 ,  H04N19/184 ,  H04N19/436

Abstract: Techniques related to parallel partitioning and coding mode selection for improved video coding throughput are discussed. Such techniques include performing parallel partitioning and coding mode selection for a lower-right coding unit of a first largest coding unit and an upper-left coding unit of a second largest coding unit to the right of the first largest coding unit and, immediately subsequent thereto, performing parallel partitioning and coding mode selection for a lower-left coding unit and an upper-right coding unit of the second largest coding unit.

公开(公告)号：US11736653B2

公开(公告)日：2023-08-22

申请号：US17898080

申请日：2022-08-29

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Paul Diefenbaugh ,  Vishal Sinha ,  Arthur Runyan ,  Gary K. Smith ,  Kathy Bui ,  Yifan Li ,  Shirley Huang Meterelliyoz

IPC: G09G5/36 ,  G09G5/399 ,  G09G5/397 ,  H04N5/073 ,  G06T1/60 ,  G09G5/00 ,  G06F3/14 ,  G09G5/393

CPC classification number: H04N5/0736 ,  G06F3/1415 ,  G06T1/60 ,  G09G5/001 ,  G09G5/363 ,  G09G5/393 ,  G09G5/399 ,  G09G5/397 ,  G09G2310/0237 ,  G09G2310/04 ,  G09G2320/062 ,  G09G2320/066 ,  G09G2360/16

Abstract: Techniques for selective display frame fetching are disclosed. Some example techniques disclosed herein cause at least one processor to at least determine if an indication of a new frame includes an indication of a flip event, and identify one or more dirty regions of the new frame based on the flip event. Disclosed example techniques also cause the at least one processor to fill a display buffer with the one or more dirty regions of the new frame, scan out the one or more dirty regions of the new frame from the display buffer to a display port, and apply an adaptive contrast and backlight enhancement based on a histogram of changes in the new frame.

公开(公告)号：US11570453B2

公开(公告)日：2023-01-31

申请号：US16920046

申请日：2020-07-02

Applicant: Intel Corporation

Inventor： Jason Tanner ,  Paul S. Diefenbaugh ,  Radhakrishnan Sankar ,  Sang-Hee Lee

IPC: H04N19/186 ,  H04N19/184 ,  H04N19/52 ,  H04L43/106 ,  H04N19/182

Abstract: Methods, apparatuses and systems may provide for a video transmitter that generates a primary bitstream based on a video signal, wherein the primary bitstream is encoded with subsampled chroma information, and detects a static condition with respect to the video signal. Additionally, a plurality of auxiliary bitstreams may be generated, in response to the static condition, based on the video signal. Each of the plurality of auxiliary bitstreams may be encoded with full resolution chroma information. In one example, a video receiver may detect that the auxiliary bitstreams are associated with the primary bitstream, decode the primary bitstream and the plurality of auxiliary bitstreams to obtain luma information and the full resolution chroma information, and multiplex the luma information with the full resolution chroma information.

公开(公告)号：US11284118B2

公开(公告)日：2022-03-22

申请号：US17111677

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Scott Janus ,  Itay Kaufman ,  Archie Sharma ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Srikanth Potluri ,  Barnan Das ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  Maria Bortman ,  Tzach Ashkenazi ,  Jonathan Distler ,  Atul Divekar ,  Mayuresh M. Varerkar ,  Narayan Biswal ,  Nilesh V. Shah ,  Atsuo Kuwahara ,  Kai Xiao ,  Jason Tanner ,  Jeffrey Tripp

IPC: H04N19/90 ,  H04N21/218 ,  G06T7/557 ,  G06T19/00 ,  G06T1/20 ,  G06T7/90

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.

公开(公告)号：US20210258616A1

公开(公告)日：2021-08-19

申请号：US17111677

申请日：2020-12-04

Applicant: Intel Corporation

Inventor： Jill Boyce ,  Scott Janus ,  Itay Kaufman ,  Archie Sharma ,  Stanley Baran ,  Michael Apodaca ,  Prasoonkumar Surti ,  Srikanth Potluri ,  Barnan Das ,  Hugues Labbe ,  Jong Dae Oh ,  Gokcen Cilingir ,  Maria Bortman ,  Tzach Ashkenazi ,  Jonathan Distler ,  Atul Divekar ,  Mayuresh M. Varerkar ,  Narayan Biswal ,  Nilesh V. Shah ,  Atsuo Kuwahara ,  Kai Xiao ,  Jason Tanner ,  Jeffrey Tripp

IPC: H04N19/90 ,  H04N21/218 ,  G06T7/557 ,  G06T19/00 ,  G06T1/20 ,  G06T7/90

Abstract: An apparatus to facilitate processing video bit stream data is disclosed. The apparatus includes one or more processors to encode surface normals data with point cloud geometry data included in the video bit stream data for reconstruction of objects within the video bit stream data based on the surface normals data and a memory communicatively coupled to the one or more processors.

公开(公告)号：US10951900B2

公开(公告)日：2021-03-16

申请号：US16015758

申请日：2018-06-22

Applicant: INTEL CORPORATION

Inventor： Zhijun Lei ,  Jason Tanner ,  Satya N. Yedidi

IPC: H04N19/159 ,  H04N19/124 ,  H04N19/176 ,  H04N19/436 ,  H04N19/122 ,  H04N19/46 ,  H04N19/11 ,  H04N19/157

Abstract: Speeding up small block intra-prediction in video coding is described herein. The system includes an encoder. The encoder is to execute intra-prediction by deriving a plurality of prediction angles, wherein the prediction angles are based on a video coding standard. The encoder is also to disable a prediction angle for a current block to eliminate a dependency on an immediate predecessor block.