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    Wrap-around contact structures for semiconductor nanowires and nanoribbons
    41.
    发明授权
    Wrap-around contact structures for semiconductor nanowires and nanoribbons 有权

    公开(公告)号：US11527640B2

    公开(公告)日：2022-12-13

    申请号：US16238978

    申请日：2019-01-03

    Applicant: Intel Corporation

    Inventor： Rishabh Mehandru ,  Tahir Ghani ,  Stephen Cea ,  Biswajeet Guha

    IPC: H01L29/775 ,  H01L29/417 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

    Abstract: Wrap-around contact structures for semiconductor nanowires and nanoribbons, and methods of fabricating wrap-around contact structures for semiconductor nanowires and nanoribbons, are described. In an example, an integrated circuit structure includes a semiconductor nanowire above a first portion of a semiconductor sub-fin. A gate structure surrounds a channel portion of the semiconductor nanowire. A source or drain region is at a first side of the gate structure, the source or drain region including an epitaxial structure on a second portion of the semiconductor sub-fin, the epitaxial structure having substantially vertical sidewalls in alignment with the second portion of the semiconductor sub-fin. A conductive contact structure is along sidewalls of the second portion of the semiconductor sub-fin and along the substantially vertical sidewalls of the epitaxial structure.

    Vertically stacked CMOS with upfront M0 interconnect
    43.
    发明授权
    Vertically stacked CMOS with upfront M0 interconnect 有权

    公开(公告)号：US11482621B2

    公开(公告)日：2022-10-25

    申请号：US16143222

    申请日：2018-09-26

    Applicant: Intel Corporation

    Inventor： Willy Rachmady ,  Patrick Morrow ,  Aaron Lilak ,  Rishabh Mehandru ,  Cheng-Ying Huang ,  Gilbert Dewey ,  Kimin Jun ,  Ryan Keech ,  Anh Phan ,  Ehren Mannebach

    IPC: H01L29/78 ,  H01L21/768 ,  H01L29/66 ,  H01L29/06

    Abstract: Embodiments include transistor devices and a method of forming the transistor devices. A transistor device includes a first dielectric over a substrate, and vias on a first metal layer, where the first metal layer is on an etch stop layer that is on the first dielectric. The transistor device also includes a second dielectric over the first metal layer, vias, and etch stop layer, where the vias include sidewalls, top surfaces, and bottom surfaces, and stacked transistors on the second dielectric and the top surfaces of the vias, where the sidewalls and top surfaces of the vias are positioned within a footprint of the stacked transistors. The stacked transistors include gate electrodes and first and second transistor layers. The first metal layer includes conductive materials including tungsten or cobalt. The footprint may include a bottom surface of the first transistor layer and a bottom surface of the gate electrodes.

    TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIAL
    44.
    发明申请
    TRANSISTOR CELLS INCLUDING A DEEP VIA LINED WITH A DIELECTRIC MATERIAL 有权

    公开(公告)号：US20220254681A1

    公开(公告)日：2022-08-11

    申请号：US17731149

    申请日：2022-04-27

    Applicant: Intel Corporation

    Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Rishabh Mehandru

    IPC: H01L21/768 ,  H01L29/78 ,  H01L27/088 ,  H01L21/8234 ,  H01L23/535 ,  H01L29/66

    Abstract: A transistor cell including a deep via that is at least partially lined with a dielectric material. The deep via may extend down to a substrate over which the transistor is disposed. The deep via may be directly connected to a terminal of the transistor, such as the source or drain, to interconnect the transistor with an interconnect metallization level disposed in the substrate under the transistor, or on at opposite side of the substrate as the transistor. Parasitic capacitance associated with the close proximity of the deep via metallization to one or more terminals of the transistor may be reduced by lining at least a portion of the deep via sidewall with dielectric material, partially necking the deep via metallization in a region adjacent to the transistor.

    STACKED TRANSISTORS WITH CONTACT LAST
    48.
    发明申请
    STACKED TRANSISTORS WITH CONTACT LAST 有权

    公开(公告)号：US20210384191A1

    公开(公告)日：2021-12-09

    申请号：US16651233

    申请日：2017-12-26

    Applicant: Intel Corporation

    Inventor： Ravi Pillarisetty ,  Willy Rachmady ,  Gilbert Dewey ,  Rishabh Mehandru ,  Jack T. Kavalieros

    IPC: H01L27/092 ,  H01L21/768 ,  H01L21/822 ,  H01L21/8238 ,  H01L23/485 ,  H01L27/06

    Abstract: An apparatus is provided which comprises: a first transistor comprising a source region and a drain region with a channel region therebetween, a first dielectric layer over the first transistor, a second transistor comprising a source region and a drain region with a channel region therebetween, wherein the second transistor is over the first dielectric layer, a second dielectric layer over the second transistor, and a contact coupled to the source region or the drain region of the first transistor, wherein the contact comprises a metal having a straight sidewall that extends from through both the first and second dielectric layers. Other embodiments are also disclosed and claimed.

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