公开(公告)号：US11894359B2

公开(公告)日：2024-02-06

申请号：US17574485

申请日：2022-01-12

Applicant: Intel Corporation

Inventor： Wilfred Gomes ,  Mark T. Bohr ,  Rajesh Kumar ,  Robert L. Sankman ,  Ravindranath V. Mahajan ,  Wesley D. McCullough

IPC: H01L23/00 ,  H01L25/18 ,  H01L23/48 ,  H01L25/00 ,  H01L23/538 ,  H01L23/522 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498

CPC classification number: H01L25/18 ,  H01L23/481 ,  H01L23/522 ,  H01L23/5383 ,  H01L24/09 ,  H01L24/17 ,  H01L25/0652 ,  H01L25/16 ,  H01L25/50 ,  H01L23/49816 ,  H01L2924/1432

Abstract: The present disclosure is directed to systems and methods of conductively coupling a plurality of relatively physically small core dies to a relatively physically larger base die using an electrical mesh network that is formed in whole or in part in, on, across, or about all or a portion of the base die. Electrical mesh networks beneficially permit the positioning of the cores in close proximity to support circuitry carried by the base die. The minimal separation between the core circuitry and the support circuitry advantageously improves communication bandwidth while reducing power consumption. Each of the cores may include functionally dedicated circuitry such as processor core circuitry, field programmable logic, memory, or graphics processing circuitry. The use of core dies beneficially and advantageously permits the use of a wide variety of cores, each having a common or similar interface to the electrical mesh network.

公开(公告)号：US11824041B2

公开(公告)日：2023-11-21

申请号：US17226967

申请日：2021-04-09

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/522 ,  H01L23/538 ,  H01L23/00

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.

公开(公告)号：US11600524B2

公开(公告)日：2023-03-07

申请号：US17147423

申请日：2021-01-12

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/768 ,  H01L29/78 ,  H01L29/49 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L21/283 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L29/08 ,  H01L29/423 ,  H01L29/16 ,  H01L29/45 ,  H01L21/285 ,  H01L23/535

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US20220028779A1

公开(公告)日：2022-01-27

申请号：US17493715

申请日：2021-10-04

Applicant: Intel Corporation

Inventor： Patrick Morrow ,  Mauro J. Kobrinsky ,  Mark T. Bohr ,  Tahir Ghani ,  Rishabh Mehandru ,  Ranjith Kumar

IPC: H01L23/528 ,  H01L21/306 ,  H01L21/8234 ,  H01L27/02 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L29/40 ,  H01L29/66 ,  H01L29/78 ,  H01L21/768 ,  H01L29/417 ,  H01L29/772 ,  H01L23/522 ,  G06F30/392 ,  G06F30/394

Abstract: Integrated circuit (IC) cell architectures including a crenellated interconnect trace layout. A crenellated trace layout may be employed where an IC cell includes transistor having a source/drain terminal interconnected through a back-side (3D) routing scheme that reduces front-side routing density for a given transistor footprint. In the crenellated layout, adjacent interconnect traces or tracks may have their ends staggered according to a crenellation phase for the cell. Crenellated tracks may intersect one cell boundary with adjacent tracks intersecting an opposite cell boundary. Track ends may be offset by at least the width of an underlying orthogonal interconnect trace. Crenellated track ends may be offset by the width of an underlying orthogonal interconnect trace and half a spacing between adjacent orthogonal interconnect traces.

公开(公告)号：US20200058791A1

公开(公告)日：2020-02-20

申请号：US16661478

申请日：2019-10-23

Applicant: INTEL CORPORATION

Inventor： Mark T. Bohr

IPC: H01L29/78 ,  H01L29/167 ,  H01L29/161 ,  H01L29/08 ,  H01L29/06 ,  H01L29/66 ,  H01L29/165 ,  H01L29/04

Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

公开(公告)号：US20190122982A1

公开(公告)日：2019-04-25

申请号：US16302692

申请日：2016-06-22

Applicant: Intel Corporation

Inventor： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr ,  Manish Chandhok

IPC: H01L23/522 ,  H01L21/762 ,  H01L21/768 ,  H01L21/8234 ,  H01L21/02

CPC classification number: H01L23/5226 ,  H01L21/02172 ,  H01L21/76224 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L21/823475 ,  H01L23/528 ,  H01L2221/1063

Abstract: An embodiment includes an apparatus comprising: a metal layer comprising a plurality of interconnect lines on a plurality of vias; an additional metal layer comprising first, second, and third interconnect lines on first, second, and third vias; the first and third vias coupling the first and third interconnect lines to two of the plurality of interconnect lines; a lateral interconnect, included entirely within the additional metal layer, directly connected to each of the first, second, and third interconnect lines; and an insulator layer included entirely between two sidewalls of the second via. Other embodiments are described herein.

公开(公告)号：US09899255B2

公开(公告)日：2018-02-20

申请号：US15528427

申请日：2014-12-23

Applicant: INTEL CORPORATION

Inventor： Rami Hourani ,  Marie Krysak ,  Florian Gstrein ,  Ruth A. Brain ,  Mark T. Bohr

IPC: H01L29/06 ,  H01L21/768 ,  H01L23/528 ,  H01L23/31

CPC classification number: H01L21/76807 ,  H01L21/76831 ,  H01L23/3171 ,  H01L23/5226 ,  H01L23/528 ,  H01L2221/1031 ,  H01L2221/1063

Abstract: Techniques are disclosed for insulating or electrically isolating select vias within a given interconnect layer, so a conductive routing can skip over those select isolated vias to reach other vias or interconnects in that same layer. Such a via blocking layer may be selectively implemented in any number of locations within a given interconnect as needed. Techniques for forming the via blocking layer are also provided, including a first methodology that uses a sacrificial passivation layer to facilitate selective deposition of insulator material that form the via blocking layer, a second methodology that uses spin-coating of wet-recessible polymeric formulations to facilitate selective deposition of insulator material that form the via blocking layer, and a third methodology that uses spin-coating of nanoparticle formulations to facilitate selective deposition of insulator material that form the via blocking layer. Harmful etching processes typically associated with conformal deposition processes is avoided.

公开(公告)号：US12288821B2

公开(公告)日：2025-04-29

申请号：US17871678

申请日：2022-07-22

Applicant: INTEL CORPORATION

Inventor： Mark T. Bohr

IPC: H01L29/78 ,  H01L29/04 ,  H01L29/06 ,  H01L29/08 ,  H01L29/161 ,  H01L29/165 ,  H01L29/167 ,  H01L29/66 ,  H01L21/84 ,  H01L29/737

Abstract: A semiconductor device having tipless epitaxial source/drain regions and a method for its formation are described. In an embodiment, the semiconductor device comprises a gate stack on a substrate. The gate stack is comprised of a gate electrode above a gate dielectric layer and is above a channel region in the substrate. The semiconductor device also comprises a pair of source/drain regions in the substrate on either side of the channel region. The pair of source/drain regions is in direct contact with the gate dielectric layer and the lattice constant of the pair of source/drain regions is different than the lattice constant of the channel region. In one embodiment, the semiconductor device is formed by using a dielectric gate stack placeholder.

公开(公告)号：US12266571B2

公开(公告)日：2025-04-01

申请号：US18374976

申请日：2023-09-29

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Tahir Ghani ,  Nadia M. Rahhal-Orabi ,  Subhash M. Joshi ,  Joseph M. Steigerwald ,  Jason W. Klaus ,  Jack Hwang ,  Ryan Mackiewicz

IPC: H01L21/768 ,  H01L21/28 ,  H01L21/283 ,  H01L21/285 ,  H01L21/311 ,  H01L23/522 ,  H01L23/528 ,  H01L23/535 ,  H01L29/08 ,  H01L29/16 ,  H01L29/423 ,  H01L29/45 ,  H01L29/49 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78

Abstract: A transistor comprises a substrate, a pair of spacers on the substrate, a gate dielectric layer on the substrate and between the pair of spacers, a gate electrode layer on the gate dielectric layer and between the pair of spacers, an insulating cap layer on the gate electrode layer and between the pair of spacers, and a pair of diffusion regions adjacent to the pair of spacers. The insulating cap layer forms an etch stop structure that is self aligned to the gate and prevents the contact etch from exposing the gate electrode, thereby preventing a short between the gate and contact. The insulator-cap layer enables self-aligned contacts, allowing initial patterning of wider contacts that are more robust to patterning limitations.

公开(公告)号：US11984430B2

公开(公告)日：2024-05-14

申请号：US18128958

申请日：2023-03-30

Applicant: Intel Corporation

Inventor： Mark T. Bohr ,  Wilfred Gomes ,  Rajesh Kumar ,  Pooya Tadayon ,  Doug Ingerly

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/522 ,  H01L23/538

CPC classification number: H01L25/0655 ,  H01L23/5226 ,  H01L23/5384 ,  H01L24/13 ,  H01L2225/06541

Abstract: Hyperchip structures and methods of fabricating hyperchips are described. In an example, an integrated circuit assembly includes a first integrated circuit chip having a device side opposite a backside. The device side includes a plurality of transistor devices and a plurality of device side contact points. The backside includes a plurality of backside contacts. A second integrated circuit chip includes a device side having a plurality of device contact points thereon. The second integrated circuit chip is on the first integrated circuit chip in a device side to device side configuration. Ones of the plurality of device contact points of the second integrated circuit chip are coupled to ones of the plurality of device contact points of the first integrated circuit chip. The second integrated circuit chip is smaller than the first integrated circuit chip from a plan view perspective.