公开(公告)号：US20170288639A1

公开(公告)日：2017-10-05

申请号：US15088830

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Adel A. ELSHERBINI ,  Feras EID ,  Baris BICEN ,  Telesphor KAMGAING ,  Vijay K. NAIR ,  Georgios C. DOGIAMIS ,  Johanna M. SWAN ,  Valluri R. RAO

IPC: H03H9/30 ,  H03H9/13

Abstract: Embodiments of the invention include a waveguide structure that includes a first piezoelectric transducer that is positioned in proximity to a first end of a cavity of an organic substrate. The first piezoelectric transducer receives an input electrical signal and generates an acoustic wave to be transmitted with a transmission medium. A second piezoelectric transducer is positioned in proximity to a second end of the cavity. The second piezoelectric transducer receives the acoustic wave from the transmission medium and generates an output electrical signal.

公开(公告)号：US20170283249A1

公开(公告)日：2017-10-05

申请号：US15088982

申请日：2016-04-01

Applicant: Intel Corporation

Inventor： Georgios C. DOGIAMIS ,  Feras EID ,  Adel A. ELSHERBINI ,  Vijay K. NAIR ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Johanna M. SWAN

IPC: B81B7/00

CPC classification number: B81C1/0015 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04

Abstract: Embodiments of the invention include a switching device that includes an electrode, a piezoelectric material coupled to the electrode, and a movable structure (e.g., cantilever, beam) coupled to the piezoelectric material. The movable structure includes a first end coupled to an anchor of a package substrate having organic layers and a second released end positioned within a cavity of the package substrate.

公开(公告)号：US20160276424A1

公开(公告)日：2016-09-22

申请号：US15169665

申请日：2016-05-31

Applicant: INTEL CORPORATION

Inventor： Andreas DUEVEL ,  Telesphor KAMGAING ,  Valluri R. RAO ,  Uwe ZILLMANN

IPC: H01L49/02 ,  H01L23/48 ,  H01L27/06 ,  H01L21/768

CPC classification number: H01L28/10 ,  H01F17/0006 ,  H01F2017/002 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5227 ,  H01L27/0688 ,  H01L27/08 ,  H01L2224/4813 ,  H01L2924/0002 ,  H01L2924/00012

Abstract: A three-dimensional inductor is formed in an integrated circuit die using conductive through-body-vias which pass through the body of the die and contact one or more metal interconnect layers on the front side of the die and terminate on the back side of the die. In another embodiment, the through-body-vias may pass through a dielectric material disposed in a plug in the body of the die. In yet another aspect, a transformer may be formed by coupling multiple inductors formed using through-body-vias. In still another aspect, a three-dimensional inductor may include conductors formed of stacks of on chip metallization layers and conductive through-layer-vias disposed in insulation layers between metallization layers. Other embodiments are described.

Abstract translation: 使用导电贯穿体通孔在集成电路管芯中形成三维电感器，该穿通体通孔穿过管芯的主体并与管芯前侧上的一个或多个金属互连层接触并终止在管芯的背面 死。 在另一个实施例中，通孔通孔可以穿过设置在管芯主体中的插塞中的电介质材料。 另一方面，变压器可以通过耦合使用通孔通孔形成的多个电感器来形成。 在另一方面，三维电感器可以包括由片上金属化层的堆叠形成的导体和设置在金属化层之间的绝缘层中的导电贯通层通孔。 描述其他实施例。

公开(公告)号：US20250007145A1

公开(公告)日：2025-01-02

申请号：US18216315

申请日：2023-06-29

Applicant: Intel Corporation

Inventor： Peter BAUMGARTNER ,  Richard GEIGER ,  Georgios C. DOGIAMIS ,  Steven CALLENDER ,  Telesphor KAMGAING ,  Jonathan C. JENSEN ,  Harald GOSSNER

IPC: H01Q1/22 ,  H01L25/10 ,  H01Q21/24

Abstract: Embodiments disclosed herein include communication dies for mm-wave and/or sub-terahertz wavelength communications. In an embodiment, a communications die comprises a substrate with a first face and a second face. In an embodiment, edge surfaces connect the first face to the second face. In an embodiment, a circuitry element is on the first face, and an antenna on at least one of the edge surfaces.

公开(公告)号：US20240364023A1

公开(公告)日：2024-10-31

申请号：US18140346

申请日：2023-04-27

Applicant: Intel Corporation

Inventor： Thomas WAGNER ,  Georg SEIDEMANN ,  Tae Young YANG ,  Harald GOSSNER ,  Telesphor KAMGAING ,  Bernd WAIDHAS

IPC: H01Q21/20 ,  H01Q5/35

CPC classification number: H01Q21/205 ,  H01Q5/35

Abstract: Embodiments disclosed herein include a communication module. In an embodiment, the communication module comprises a package substrate, and a die on the package substrate. In an embodiment, a plurality of antennas are around the die. In an embodiment, the plurality of antennas are coupled to the die by a plurality of traces, and heights of each of the plurality of antennas is greater than a thickness of the traces.

公开(公告)号：US20230420354A1

公开(公告)日：2023-12-28

申请号：US17848643

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Telesphor KAMGAING ,  Chee Kheong YOON ,  Chu Aun LIM ,  Eng Huat GOH ,  Min Suet LIM ,  Kavitha NAGARAJAN ,  Jooi Wah WONG

IPC: H01L23/498 ,  H01L21/48 ,  H05K1/18

CPC classification number: H01L23/49838 ,  H01L23/49816 ,  H01L23/49827 ,  H01L21/4853 ,  H05K1/181 ,  H01L23/49822 ,  H05K2201/10378 ,  H05K2201/10734

Abstract: Embodiments herein relate to systems, apparatuses, techniques, or processes directed to an electrical conductor, or power corridor, on the outside of a package substrate, wherein the electrical conductor is raised, or extends from a surface of the package substrate. In embodiments, this electrical conductor may be used to reduce the number of layers required within the package substrate by removing power planes within the substrate to the electrical conductors on the surface of the package. Other embodiments may be described and/or claimed.

公开(公告)号：US20230420350A1

公开(公告)日：2023-12-28

申请号：US17848630

申请日：2022-06-24

Applicant: Intel Corporation

Inventor： Kavitha NAGARAJAN ,  Eng Huat GOH ,  Min Suet LIM ,  Telesphor KAMGAING ,  Chee Kheong YOON ,  Jooi Wah WONG ,  Chu Aun LIM

IPC: H01L23/498 ,  H01L25/065 ,  H01L21/48

CPC classification number: H01L23/49833 ,  H01L25/0652 ,  H01L23/49816 ,  H01L24/16 ,  H01L23/49838 ,  H01L21/4853 ,  H01L23/49822

Abstract: Embodiments herein relate to systems, apparatuses, techniques or processes for packages that include a die complex with a base die that is coupled with a HDP substrate that in turn is coupled with an mSAP board. The HDP substrate may have a small trace width and trace spacing, for example three μm or less, that enable the HDP substrate to be used as a pitch translator between the base die and the mSAP board, for example between a 110 μm pitch and a 210 μm pitch. One or more DRAM modules may be coupled with the mSAP board. The configuration has a reduced overall package height. Other embodiments may be described and/or claimed.

公开(公告)号：US20230395577A1

公开(公告)日：2023-12-07

申请号：US17833592

申请日：2022-06-06

Applicant: Intel Corporation

Inventor： Eng Huat GOH ,  Telesphor KAMGAING ,  Jooi Wah WONG ,  Min Suet LIM ,  Chee Kheong YOON ,  Kavitha NAGARAJAN ,  Chu Aun LIM

IPC: H01L25/10 ,  H01L25/065 ,  H01L25/00

CPC classification number: H01L25/105 ,  H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/06586

Abstract: Embodiments disclosed herein include an electronic package. In an embodiment, the electronic package comprises a package substrate with a cutout. In an embodiment, pads are adjacent to the cutout. In an embodiment, a memory die stack is on the package substrate, where the memory die stack is electrically coupled to the pads by routing in the package substrate. In an embodiment, a die is over the cutout, where the die is supported by the pads.

公开(公告)号：US20230361802A1

公开(公告)日：2023-11-09

申请号：US18029932

申请日：2020-11-03

Applicant: Intel Corporation

Inventor： Jayprakash THAKUR ,  Ofir DEGANI ,  Ronen KRONFELD ,  Ehud RESHEF ,  Seong-Youp J. SUH ,  Tal SHOSHANA ,  Eytan MANN ,  Maruti TAMRAKAR ,  Ashoke RAVI ,  Jose Rodrigo CAMACHO PEREZ ,  Timo Sakari HUUSARI ,  Eli BOROKHOVICH ,  Amir RUBIN ,  Ofer BENJAMIN ,  Tae Young YANG ,  Harry SKINNER ,  Kwan ho LEE ,  Jaejin LEE ,  Dong-Ho Han ,  Shahar GROSS ,  Eran SEGEV ,  Telesphor KAMGAING

IPC: H04B1/40

CPC classification number: H04B1/40

Abstract: In various aspects, a radio frequency circuit is provided. The radio frequency circuit may include a substrate that may include a radio frequency front-end to antenna (RF FE-to-Ant) connector. The RF FE-to-Ant connector may include a conductor track structure and a substrate connection structure coupled to the conductor track structure. The substrate may include radio frequency front-end circuitry monolithically integrated in the substrate. The substrate connection structure may include at least one of a solderable structure, a weldable structure, or an adherable structure. The substrate connection structure may be configured to form at least one radio frequency signal interface with an antenna circuit connection structure of a substrate-external antenna circuit. The substrate may include an edge region. The substrate connection structure may be disposed in the edge region.

公开(公告)号：US20230197646A1

公开(公告)日：2023-06-22

申请号：US17557948

申请日：2021-12-21

Applicant: Intel Corporation

Inventor： Aleksandar ALEKSOV ,  Telesphor KAMGAING ,  Georgios C. DOGIAMIS ,  Neelam PRABHU GAUNKAR ,  Veronica STRONG ,  Brandon RAWLINGS ,  Andrew P. COLLINS ,  Arghya SAIN ,  Sivaseetharaman PANDI

IPC: H01L23/66 ,  H01L23/15 ,  H01L23/498 ,  H01P3/08

CPC classification number: H01L23/66 ,  H01L23/15 ,  H01L23/49827 ,  H01L23/49838 ,  H01P3/081 ,  H01L2223/6616 ,  H01L2223/6627 ,  H01L2223/6638

Abstract: Embodiments disclosed herein include electronic packages. In an embodiment, the electronic package comprises a substrate with a first surface and a second surface opposite from the first surface, where the substrate comprises glass. In an embodiment, the electronic package further comprises a trace embedded in the substrate, where a width of the trace is less than a height of the trace. In an embodiment, the electronic package further comprises a first layer on the first surface of the substrate, where the first layer is a dielectric buildup film, and a second layer on the second surface of the substrate, where the second layer is the dielectric buildup film.