公开(公告)号：US08775833B2

公开(公告)日：2014-07-08

申请号：US13780066

申请日：2013-02-28

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Doron Rajwan ,  Eliezer Weissmann ,  Nadav Shulman

IPC: G06F1/00 ,  G06F15/00 ,  G05D3/12

CPC classification number: G06F1/26 ,  G06F1/3243 ,  G06F9/5094 ,  Y02D10/152

Abstract: In one embodiment, the present invention includes a method for determining a power budget for a multi-domain processor for a current time interval, determining a portion of the power budget to be allocated to first and second domains of the processor, and controlling a frequency of the domains based on the allocated portions. Such determinations and allocations can be dynamically performed during runtime of the processor. Other embodiments are described and claimed.

公开(公告)号：US20240004442A1

公开(公告)日：2024-01-04

申请号：US18456965

申请日：2023-08-28

Applicant: Intel Corporation

Inventor： Muhammad Abozaed ,  Eugene Gorbatov ,  Gaurav Khanna ,  Avinash N. Ananthakrishnan

IPC: G06F1/20 ,  G06F9/48 ,  G06F1/3206

CPC classification number: G06F1/206 ,  G06F9/4843 ,  G06F1/3206 ,  G06F9/4893 ,  Y02D10/00

Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

公开(公告)号：US11775036B2

公开(公告)日：2023-10-03

申请号：US17867187

申请日：2022-07-18

Applicant: Intel Corporation

Inventor： Muhammad Abozaed ,  Eugene Gorbatov ,  Gaurav Khanna ,  Avinash N. Ananthakrishnan

IPC: G06F1/26 ,  G06F1/32 ,  G06F1/20 ,  G06F9/48 ,  G06F1/3206

CPC classification number: G06F1/206 ,  G06F1/3206 ,  G06F9/4843 ,  G06F9/4893 ,  Y02D10/00

Abstract: Embodiments are generally directed to enhanced power management for support of priority system events. An embodiment of a system includes a processing element; a memory including a registry for information regarding one or more system events that are designated as priority events; a mechanism to track operation of events that requires Turbo mode operation for execution; and a power control unit to implement a power management algorithm. The system is to maintain an first energy budget and a second residual energy budget for operation in a Turbo power mode, and wherein the power management algorithm is to determine whether to authorize execution of a detected system event in the Turbo power mode based on the second residual energy budget upon determining that the first energy budget is not sufficient for execution of the detected system event and that the detected system event is designated as a priority event. Priority designations for the priority events may include a first High Priority designation and a second Critical designation.

公开(公告)号：US20230297424A1

公开(公告)日：2023-09-21

申请号：US18322636

申请日：2023-05-24

Applicant: Intel Corporation

Inventor： Praveen Kumar Gupta ,  Avinash N. Ananthakrishnan ,  Eugene Gorbatov ,  Stephen H. Gunther

IPC: G06F9/48 ,  G06F1/10 ,  G06F1/08 ,  G06F1/3296

CPC classification number: G06F9/4893 ,  G06F1/10 ,  G06F1/08 ,  G06F1/3296 ,  G06F1/324

Abstract: In one embodiment, a processor includes a power controller having a resource allocation circuit. The resource allocation circuit may: receive a power budget for a first core and at least one second core and scale the power budget based at least in part on at least one energy performance preference value to determine a scaled power budget; determine a first maximum operating point for the first core and a second maximum operating point for the at least one second core based at least in part on the scaled power budget; determine a first efficiency value for the first core based at least in part on the first maximum operating point for the first core and a second efficiency value for the at least one second core based at least in part on the second maximum operating point for the at least one second core; and report a hardware state change to an operating system scheduler based on the first efficiency value and the second efficiency value. Other embodiments are described and claimed.

公开(公告)号：US11481013B2

公开(公告)日：2022-10-25

申请号：US16880167

申请日：2020-05-21

Applicant: Intel Corporation

Inventor： Doron Rajwan ,  Efraim Rotem ,  Eliezer Weissmann ,  Avinash N. Ananthakrishnan ,  Dorit Shapira

IPC: G06F15/76 ,  G06F1/3228 ,  G06F1/324 ,  G06F1/3237 ,  G06F1/3203 ,  G06F1/3234 ,  G06F1/3293 ,  G06F30/34 ,  G06F119/06 ,  G06F119/08

Abstract: In an embodiment, a processor includes processing cores, and a central control unit to: concurrently execute an outer control loop and an inner control loop, wherein the outer control loop is to monitor the processor as a whole, and wherein the inner control loop is to monitor a first processing core included in the processor; determine, based on the outer control loop, a first control action for the first processing core included in the processor; determine, based on the inner control loop, a second control action for the first processing core included in the processor; based on a comparison of the first control action and the second control action, select one of the first control action and the second control action as a selected control action; and apply the selected control action to the first processing core. Other embodiments are described and claimed.

公开(公告)号：US20220291732A1

公开(公告)日：2022-09-15

申请号：US17828471

申请日：2022-05-31

Applicant: Intel Corporation

Inventor： Anupama Suryanarayanan ,  Avinash N. Ananthakrishnan ,  Chinmay Ashok ,  Jeremy J. Shrall

IPC: G06F1/26 ,  G06F1/3287 ,  G06F13/42 ,  G06F1/32 ,  G06F1/3203 ,  G06F1/3296 ,  G06F9/46 ,  G06F1/3234 ,  G06F30/00

Abstract: In one embodiment, a processor includes: a plurality of cores; a first storage to store parameter information for a voltage regulator to couple to the processor via a voltage regulator interface; and a power controller to control power consumption of the processor. The power controller may determine a performance state for one or more cores of the processor and include a hardware logic to generate a message for the voltage regulator based at least in part on the parameter information, where this message is to cause the voltage regulator to output a voltage to enable the one or more cores to operate at the performance state. Other embodiments are described and claimed.

公开(公告)号：US11442529B2

公开(公告)日：2022-09-13

申请号：US16412606

申请日：2019-05-15

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Ameya Ambardekar ,  Ankush Varma ,  Nimrod Angel ,  Nir Rosenzweig ,  Arik Gihon ,  Alexander Gendler ,  Rachid E. Rayess ,  Tamir Salus

IPC: G06F1/00 ,  G06F1/3234 ,  G06F1/3296 ,  G06F9/38 ,  G06F11/34

Abstract: In one embodiment, an apparatus comprises: a plurality of intellectual property (IP) circuits, each of the plurality of IP circuits including a configuration register to store a dynamic current budget; and a power controller coupled to the plurality of IP circuits, the power controller including a dynamic current sharing control circuit to receive current throttling hint information regarding a workload to be executed on at least some of the plurality of IP circuits and generate the dynamic current budget for each of the plurality of IP circuits based at least in part thereon. Other embodiments are described and claimed.

公开(公告)号：US10474218B2

公开(公告)日：2019-11-12

申请号：US16223794

申请日：2018-12-18

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Efraim Rotem ,  Eliezer Weissmann ,  Doron Rajwan ,  Nadav Shulman ,  Alon Naveh ,  Hisham Abu-Salah

IPC: G06F12/00 ,  G06F1/3234 ,  G06F12/0864 ,  G06F12/084 ,  G06F1/28 ,  G06F12/0802 ,  G06F1/3287 ,  G06F12/0846

Abstract: In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.

公开(公告)号：US10345884B2

公开(公告)日：2019-07-09

申请号：US15238717

申请日：2016-08-16

Applicant: Intel Corporation

Inventor： Ankush Varma ,  Krishnakanth V. Sistla ,  Martin T. Rowland ,  Chris Poirier ,  Eric J. Dehaemer ,  Avinash N. Ananthakrishnan ,  Jeremy J. Shrall ,  Xiuting C. Man ,  Stephen H. Gunther ,  Krishna K. Rangan ,  Devadatta V. Bodas ,  Don C. Soltis, Jr. ,  Hang T. Nguyen ,  Cyprian W. Woo ,  Thi Dang

IPC: G06F9/00 ,  G06F1/3234 ,  G06F1/20 ,  G06F1/3206 ,  G06F1/28

Abstract: One embodiment of an apparatus includes a semiconductor chip having a processor and an on-die non-volatile storage resource. The on-die non-volatile storage may store different, appropriate performance related information for different configurations and usage cases of the processor for a same performance state of the processor.

公开(公告)号：US20190102221A1

公开(公告)日：2019-04-04

申请号：US15720296

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Avinash N. Ananthakrishnan ,  Vijay Dhanraj ,  Russell J. Fenger ,  Vivek Garg ,  Eugene Gorbatov ,  Stephen H. Gunter ,  Monica Gupta ,  Efraim Rotem ,  Krishnakanth V. Sistla ,  Guy M. Therien ,  Ankush Varma ,  Eliezer Weissmann

IPC: G06F9/48 ,  G06F9/30

Abstract: In an embodiment, a processor includes a plurality of processing engines (PEs) to execute threads, and a guide unit. The guide unit is to: monitor execution characteristics of the plurality of PEs and the threads; generate a plurality of PE rankings, each PE ranking including the plurality of PEs in a particular order; and store the plurality of PE rankings in a memory to be provided to a scheduler, the scheduler to schedule the threads on the plurality of PEs using the plurality of PE rankings. Other embodiments are described and claimed.