公开(公告)号：US10707319B2

公开(公告)日：2020-07-07

申请号：US15067047

申请日：2016-03-10

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Mark L. Doczy ,  Suman Datta ,  Justin K. Brask ,  Matthew V. Metz

IPC: H01L21/8234 ,  H01L29/78 ,  H01L29/51 ,  H01L21/28 ,  H01L21/8238 ,  H01L29/49 ,  H01L29/66

Abstract: A method of manufacturing a semiconductor device and a novel semiconductor device are disclosed herein. An exemplary method includes sputtering a capping layer in-situ on a gate dielectric layer, before any high temperature processing steps are performed. The method includes depositing a dielectric layer on a substrate, followed by deposition of a capping layer in-situ over the dielectric layer prior to any high temperature processing.

公开(公告)号：US10651313B2

公开(公告)日：2020-05-12

申请号：US16325423

申请日：2016-09-30

Applicant: Intel Corporation

Inventor： Cheng-Ying Huang ,  Matthew V. Metz ,  Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Sean T. Ma

IPC: H01L27/088 ,  H01L29/786 ,  H01L29/06 ,  H01L29/423 ,  B82Y10/00 ,  H01L29/66 ,  H01L29/775 ,  H01L29/78 ,  H01L29/417 ,  H01L21/8234 ,  H01L29/08 ,  H01L27/24

Abstract: An embodiment includes a transistor comprising: first, second, and third layers each including a group III-V material; a channel included in the second layer, which is between the first and third layers; and a gate having first and second gate portions; wherein (a)(i) the first and third layers are doped, (a)(ii) the channel is between the first and second gate portions and the second gate portion is between the channel and a substrate, (a)(iii) a first axis intersects the first, second, and third layers but not the first gate portion, and (a)(iv) a second axis, parallel to the first axis, intersects the first and second gate portions and the channel. Other embodiments are described herein.

公开(公告)号：US20200098753A1

公开(公告)日：2020-03-26

申请号：US16141000

申请日：2018-09-25

Applicant: INTEL CORPORATION

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Jack T. Kavalieros ,  Cheng-Ying Huang ,  Matthew V. Metz ,  Sean T. Ma ,  Harold Kennel ,  Tahir Ghani ,  Abhishek A. Sharma

IPC: H01L27/092 ,  H01L29/66 ,  H01L29/267 ,  H01L29/10 ,  H01L29/51 ,  H01L21/02 ,  H01L21/28

Abstract: Techniques are disclosed for integrating semiconductor oxide materials as alternate channel materials for n-channel devices in integrated circuits. The semiconductor oxide material may have a wider band gap than the band gap of silicon. Additionally or alternatively, the high mobility, wide band gap semiconductor oxide material may have a higher electron mobility than silicon. The use of such semiconductor oxide materials can provide improved NMOS channel performance in the form of less off-state leakage and, in some instances, improved electron mobility as compared to silicon NMOS channels.

公开(公告)号：US20200020805A1

公开(公告)日：2020-01-16

申请号：US16490502

申请日：2017-03-31

Applicant: Intel Corporation

Inventor： Ravi Pillarisetty ,  Abhishek A. Sharma ,  Van H. Le ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L29/78 ,  H01L29/66 ,  H01L29/51

Abstract: Disclosed are systems, methods, and apparatus directed to the fabrication of vertical field effect transistors (VFETs) and VFETs with self-aligned wordlines. In one embodiment, the source and/or drain of the VFETs can include n-doped silicon. In one embodiment, the VFETs can include a channel that can be made of intrinsic silicon. In one embodiment, the source, drain, and/or channel can be deposited using physical vapor deposition (PVD), chemical vapor deposition (CVD), molecular beam chemical vapor deposition (MOCVD), and/or atomic layer deposition (ALD), and the like. In one embodiment, an STI process can be used to fabricate one or more recesses, which can reach the drains of the VFETs. In one embodiment, the systems, methods, and apparatus can permit the self-alignment of one or more wordlines of the VFETs with the one or more fins, and/or gate metals and gate materials of the VFETs.

公开(公告)号：US10483353B2

公开(公告)日：2019-11-19

申请号：US15778863

申请日：2015-12-24

Applicant: INTEL CORPORATION

Inventor： Chandra S. Mohapatra ,  Glenn A. Glass ,  Anand S. Murthy ,  Karthik Jambunathan ,  Willy Rachmady ,  Gilbert Dewey ,  Tahir Ghani ,  Jack T. Kavalieros

IPC: H01L29/78 ,  H01L29/10 ,  H01L21/8238 ,  H01L29/423 ,  H01L29/66 ,  H01L29/739 ,  H01L27/092 ,  H01L29/786

Abstract: Techniques are disclosed for forming transistor structures including tensile-strained germanium (Ge) channel material. The transistor structures may be used for either or both of n-type and p-type transistor devices, as tensile-strained Ge has very high carrier mobility properties suitable for both types. Thus, a simplified CMOS integration scheme may be achieved by forming n-MOS and p-MOS devices included in the CMOS device using the techniques described herein. In some cases, the tensile-strained Ge may be achieved by epitaxially growing the Ge material on a group III-V material having a lattice constant that is higher than that of Ge and/or by applying a macroscopic 3-point bending to the die on which the transistor is formed. The techniques may be used to form transistors having planar or non-planar configurations, such as finned configurations (e.g., finFET or tri-gate) or gate-all-around (GAA) configurations (including at least one nanowire).

公开(公告)号：US10461082B2

公开(公告)日：2019-10-29

申请号：US15577734

申请日：2015-06-26

Applicant: Intel Corporation

Inventor： Willy Rachmady ,  Matthew V. Metz ,  Gilbert Dewey ,  Chandra S. Mohapatra ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Nadia M. Rahhal-Orabi ,  Tahir Ghani

IPC: H01L27/092 ,  H01L21/8238 ,  H01L21/8258 ,  H01L29/10

Abstract: Non-silicon fin structures extend from a crystalline heteroepitaxial well material in a well recess of a substrate. III-V finFETs may be formed on the fin structures within the well recess while group IV finFETs are formed in a region of the substrate adjacent to the well recess. The well material may be electrically isolated from the substrate by an amorphous isolation material surrounding pillars passing through the isolation material that couple the well material to a seeding surface of the substrate and trap crystal growth defects. The pillars may be expanded over the well-isolation material by lateral epitaxial overgrowth, and the well recess filled with a single crystal of high quality. Well material may be planarized with adjacent substrate regions. N-type fin structures may be fabricated from the well material in succession with p-type fin structures fabricated from the substrate, or second epitaxial well.

公开(公告)号：US10411007B2

公开(公告)日：2019-09-10

申请号：US15755490

申请日：2015-09-25

Applicant: Intel Corporation

Inventor： Gilbert Dewey ,  Willy Rachmady ,  Matthew V. Metz ,  Chandra S. Mohapatra ,  Sean T. Ma ,  Jack T. Kavalieros ,  Anand S. Murthy ,  Tahir Ghani

IPC: H01L27/06 ,  H01L29/66 ,  H01L21/8252 ,  H01L29/775 ,  H01L29/06 ,  H01L29/205 ,  H01L21/8258 ,  H01L29/16 ,  H01L29/423 ,  H01L29/78 ,  H01L29/786 ,  B82Y10/00 ,  H01L27/092 ,  H01L21/8238

Abstract: Monolithic FETs including a channel region in a first semiconductor material disposed over a substrate. While a mask, such as a gate stack or sacrificial gate stack, is covering a channel region, a semiconductor spacer of a semiconductor material with a band offset relative to the channel material is grown, for example on at least a drain end of the channel region to introduce at least one charge carrier-blocking band offset between the channel semiconductor and a drain region of a third III-V semiconductor material. In some N-type transistor embodiments, the carrier-blocking band offset is a conduction band offset of at least 0.1 eV. A wider band gap and/or a blocking conduction band offset may contribute to reduced gate induced drain leakage (GIDL). Source/drain regions couple electrically to the channel region through the semiconductor spacer, which may be substantially undoped (i.e. intrinsic) or doped. In some embodiments, the semiconductor spacer growth is integrated into a gate-last, source/drain regrowth finFET fabrication process.

公开(公告)号：US20190259844A1

公开(公告)日：2019-08-22

申请号：US15899590

申请日：2018-02-20

Applicant: Intel Corporation

Inventor： Abhishek A. Sharma ,  Tahir Ghani ,  Jack T. Kavalieros ,  Gilbert Dewey ,  Van H. Le ,  Lawrence D. Wong ,  Christopher J. Jezewski

IPC: H01L29/417 ,  H01L29/786 ,  H01L23/29 ,  H01L29/423 ,  H01L29/49 ,  H01L29/66

Abstract: Disclosed herein are transistor electrode-channel arrangements, and related methods and devices. For example, in some embodiments, a transistor electrode-channel arrangement may include a channel material, source/drain electrodes provided over the channel material, and a sealant at least partially enclosing one or more of the source/drain electrodes, wherein the sealant includes one or more metallic conductive materials.

公开(公告)号：US10373977B2

公开(公告)日：2019-08-06

申请号：US15576393

申请日：2015-06-26

Applicant: INTEL CORPORATION

Inventor： Glenn A. Glass ,  Anand S. Murthy ,  Daniel B. Aubertine ,  Tahir Ghani ,  Jack T. Kavalieros ,  Benjamin Chu-Kung ,  Chandra S. Mohapatra ,  Karthik Jambunathan ,  Gilbert Dewey ,  Willy Rachmady

IPC: H01L27/12 ,  H01L29/78 ,  H01L21/84 ,  H01L29/66 ,  H01L21/762 ,  H01L29/06 ,  H01L29/161 ,  H01L29/20

Abstract: Techniques are disclosed for customization of fin-based transistor devices to provide a diverse range of channel configurations and/or material systems, and within the same integrated circuit die. In accordance with an embodiment, sacrificial fins are cladded and then removed thereby leaving the cladding layer as a pair of standalone fins. Once the sacrificial fin areas are filled back in with a suitable insulator, the resulting structure is fin-on-insulator. The new fins can be configured with any materials by using such a cladding-on-core approach. The resulting fin-on-insulator structure is favorable, for instance, for good gate control while eliminating or otherwise reducing sub-channel source-to-drain (or drain-to-source) leakage current. In addition, parasitic capacitance from channel-to-substrate is significantly reduced. The sacrificial fins can be thought of as cores and can be implemented, for example, with material native to the substrate or a replacement material that enables low-defect exotic cladding materials combinations.

公开(公告)号：US10319646B2

公开(公告)日：2019-06-11

申请号：US15498280

申请日：2017-04-26

Applicant: Intel Corporation

Inventor： Marko Radosavljevic ,  Ravi Pillarisetty ,  Gilbert Dewey ,  Niloy Mukherjee ,  Jack Kavalieros ,  Willy Rachmady ,  Van Le ,  Benjamin Chu-Kung ,  Matthew Metz ,  Robert Chau

IPC: B82Y10/00 ,  H01L21/02 ,  H01L21/84 ,  H01L27/12 ,  H01L29/06 ,  H01L29/16 ,  H01L29/20 ,  H01L29/66 ,  H01L29/78 ,  H01L21/306 ,  H01L27/092 ,  H01L29/205 ,  H01L29/423 ,  H01L29/775 ,  H01L29/786 ,  H01L21/8238 ,  H01L21/8258

Abstract: Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.