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    DYNAMICALLY COMPOSABLE COMPUTING SYSTEM, A DATA CENTER, AND METHOD FOR DYNAMICALLY COMPOSING A COMPUTING SYSTEM
    41.
    发明申请
    DYNAMICALLY COMPOSABLE COMPUTING SYSTEM, A DATA CENTER, AND METHOD FOR DYNAMICALLY COMPOSING A COMPUTING SYSTEM 审中-公开

    公开(公告)号：US20180284996A1

    公开(公告)日：2018-10-04

    申请号：US15474044

    申请日：2017-03-30

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Mark Schmisseur ,  Karthik Kumar ,  Thomas Willhalm ,  Lidia Warnes

    IPC: G06F3/06

    CPC classification number: G06F3/067 ,  G06F3/0605 ,  G06F3/0631 ,  G06F9/50

    Abstract: The present disclosure relates to a dynamically composable computing system. The dynamically composable computing system comprises at least one compute sled including a set of respective local computing hardware resources; a plurality of disaggregated memory modules; at least one disaggregated memory acceleration logic configured to perform one or more predefined computations on data stored in one or more of the plurality of disaggregated memory modules; and a resource manager module configured to assemble a composite computing node by associating, in accordance with requirements of a user, at least one of the plurality of disaggregated memory modules with the disaggregated memory acceleration logic to provide at least one accelerated disaggregated memory module and connecting the least one accelerated disaggregated memory module to the compute sled.

    Technologies for fabric supported sequencers in distributed architectures
    43.
    发明授权
    Technologies for fabric supported sequencers in distributed architectures 有权

    公开(公告)号：US10038767B2

    公开(公告)日：2018-07-31

    申请号：US15260613

    申请日：2016-09-09

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Raj K. Ramanujan ,  Daniel Rivas Barragan

    IPC: H04L12/50 ,  H04L29/08 ,  H04L1/16

    CPC classification number: H04L69/324 ,  G06F15/173 ,  H04L1/1642 ,  H04L12/50 ,  H04L45/28 ,  H04L45/745 ,  H04L49/00

    Abstract: Technologies for using fabric supported sequencers in fabric architectures includes a network switch communicatively coupled to a plurality of computing nodes. The network switch is configured to receive an sequencer access message from one of the plurality of computing nodes that includes an identifier of a sequencing counter corresponding to a sequencer session and one or more operation parameters. The network switch is additionally configured to perform an operation on a value associated with the identifier of the sequencing counter as a function of the one or more operation parameters, increment the identifier of the sequencing counter, and associate a result of the operation with the incremented identifier of the sequencing counter. The network switch is further configured to transmit an acknowledgment of successful access to the computing node that includes the result of the operation and the incremented identifier of the sequencing counter. Other embodiments are described herein.

    Technologies for application validation in persistent memory systems
    45.
    发明授权
    Technologies for application validation in persistent memory systems 有权
    持久性存储器系统中的应用验证技术

    公开(公告)号：US09535820B2

    公开(公告)日：2017-01-03

    申请号：US14670965

    申请日：2015-03-27

    Applicant: Intel Corporation

    Inventor： Philip R. Lantz ,  Thomas Willhalm ,  Kirill Instrumentov ,  Karthik Kumar

    IPC: G06F9/44 ,  G06F11/36

    CPC classification number: G06F11/3688 ,  G06F11/3648

    Abstract: Technologies for software testing include a computing device having persistent memory that includes a platform simulator and an application or other code module to be tested. The computing device generates a checkpoint for the application at a test location using the platform simulator. The computing device executes the application from the test location to an end location and traces all writes to persistent memory using the platform simulator. The computing device generates permutations of persistent memory writes that are allowed by the hardware specification of the computing device simulated by the platform simulator. The computing device replays each permutation from the checkpoint, simulates a power failure, and then invokes a user-defined test function using the platform simulator. The computing device may test different permutations of memory writes until the application's use of persistent memory is validated. Other embodiments are described and claimed.

    Abstract translation: 用于软件测试的技术包括具有持久存储器的计算设备，其包括平台模拟器和要测试的应用或其他代码模块。 计算设备使用平台模拟器在测试位置生成应用程序的检查点。 计算设备从测试位置执行应用程序到终端位置，并使用平台模拟器跟踪对持久存储器的所有写入。 计算设备产生由平台模拟器模拟的计算设备的硬件规范允许的持久存储器写入的排列。 计算设备从检查点重播每个置换，模拟电源故障，然后使用平台模拟器调用用户定义的测试功能。 计算设备可以测试存储器写入的不同排列，直到应用程序使用永久存储器被验证为止。 描述和要求保护其他实施例。

    System, apparatus and methods for handling consistent memory transactions according to a CXL protocol
    47.
    发明授权
    System, apparatus and methods for handling consistent memory transactions according to a CXL protocol 有权

    公开(公告)号：US12189545B2

    公开(公告)日：2025-01-07

    申请号：US17443379

    申请日：2021-07-26

    Applicant: Intel Corporation

    Inventor： Karthik Kumar ,  Francesc Guim Bernat

    IPC: G06F13/16 ,  G06F13/40 ,  G06F13/42

    Abstract: In one embodiment, an apparatus includes: an interface to couple a plurality of devices of a system and enable communication according to a Compute Express Link (CXL) protocol. The interface may receive a consistent memory request having a type indicator to indicate a type of consistency to be applied to the consistent memory request. A request scheduler coupled to the interface may receive the consistent memory request and schedule it for execution according to the type of consistency, based at least in part on a priority of the consistent memory request and one or more pending consistent memory requests. Other embodiments are described and claimed.

    SCALABLE EDGE COMPUTING
    48.
    发明申请
    SCALABLE EDGE COMPUTING 有权

    公开(公告)号：US20240396852A1

    公开(公告)日：2024-11-28

    申请号：US18792276

    申请日：2024-08-01

    Applicant: Intel Corporation

    Inventor： Francesc Guim Bernat ,  Karthik Kumar ,  Thomas Willhalm ,  Mark A. Schmisseur ,  Timothy Verrall

    IPC: H04L47/765 ,  G06F9/50 ,  G06N20/00 ,  H04L47/70 ,  H04L47/83

    Abstract: There is disclosed in one example an application-specific integrated circuit (ASIC), including: an artificial intelligence (AI) circuit; and circuitry to: identify a flow, the flow including traffic diverted from a core cloud service of a network to be serviced by an edge node closer to an edge of the network than to the core of the network; receive telemetry related to the flow, the telemetry including fine-grained and flow-level network monitoring data for the flow; operate the AI circuit to predict, from the telemetry, a future service-level demand for the edge node; and cause a service parameter of the edge node to be tuned according to the prediction.

    Adaptive routing for pooled and tiered data architectures
    50.
    发明授权
    Adaptive routing for pooled and tiered data architectures 有权

    公开(公告)号：US12130754B2

    公开(公告)日：2024-10-29

    申请号：US16995481

    申请日：2020-08-17

    Applicant: Intel Corporation

    Inventor： Karthik Kumar ,  Francesc Guim Bernat

    IPC: G06F12/14 ,  G06F12/06 ,  G06F12/0813 ,  G06F12/0891

    CPC classification number: G06F12/1441 ,  G06F12/0646 ,  G06F12/0813 ,  G06F12/0891 ,  G06F12/1483

    Abstract: Examples described herein relate to a network device apparatus that includes a packet processing circuitry configured to determine if target data associated with a memory access request is stored in a different device than that identified in the memory access request and based on the target data associated with the memory access request identified as stored in a different device than that identified in the memory access request, cause transmission of the memory access request to the different device. In some examples, the memory access request comprises an identifier of a requester of the memory access request and the identifier comprises a Process Address Space identifier (PASID) and wherein the configuration that a redirection operation is permitted to be performed for a memory access request is based at least on the identifier. In some examples, the packet processing circuitry is to: based on configuration of a redirection operation not to be performed for the memory access request, cause transmission of the memory access request to a device identified in the memory access request.

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