公开(公告)号：US11321910B2

公开(公告)日：2022-05-03

申请号：US16746636

申请日：2020-01-17

Applicant: Intel Corporation

Inventor： Michael Doyle ,  Karthik Vaidyanathan

IPC: G06T15/10 ,  G06T9/00 ,  G06T15/06 ,  G06T1/60

Abstract: Apparatus and method for efficient BVH construction. For example, one embodiment of an apparatus comprises: a memory to store graphics data for a scene including a plurality of primitives in a scene at a first precision; a geometry quantizer to read vertices of the primitives at the first precision and to adaptively quantize the vertices of the primitives to a second precision associated with a first local coordinate grid of a first BVH node positioned within a global coordinate grid, the second precision lower than the first precision; a BVH builder to determine coordinates of child nodes of the first BVH node by performing non-spatial-split binning or spatial-split binning for the first BVH node using primitives associated with the first BVH node, the BVH builder to determine final coordinates for the child nodes based, at least in part, on an evaluation of surface areas of different bounding boxes generated for each of the child node.

公开(公告)号：US11315304B2

公开(公告)日：2022-04-26

申请号：US17003011

申请日：2020-08-26

Applicant: INTEL CORPORATION

Inventor： Scott Janus ,  Prasoonkumar Surti ,  Karthik Vaidyanathan ,  Alexey Supikov ,  Gabor Liktor ,  Carsten Benthin ,  Philip Laws ,  Michael Doyle

IPC: G06T15/06 ,  G06T17/00 ,  G06T1/60 ,  G06T15/00

Abstract: Apparatus and method for a hierarchical beam tracer. For example, one embodiment of an apparatus comprises: a beam generator to generate beam data associated with a beam projected into a graphics scene; a bounding volume hierarchy (BVH) generator to generate BVH data comprising a plurality of hierarchically arranged BVH nodes; a hierarchical beam-based traversal unit to determine whether the beam intersects a current BVH node and, if so, to responsively subdivide the beam into N child beams to test against the current BVH node and/or to traverse further down the BVH hierarchy to select a new BVH node, wherein the hierarchical beam-based traversal unit is to iteratively subdivide successive intersecting child beams and/or to continue to traverse down the BVH hierarchy until a leaf node is reached with which at least one final child beam is determined to intersect; the hierarchical beam-based traversal unit to generate a plurality of rays within the final child beam; and intersection hardware logic to perform intersection testing for any rays intersecting the leaf node, the intersection testing to determine intersections between the rays intersecting the leaf node and primitives bounded by the leaf node.

公开(公告)号：US20220084156A1

公开(公告)日：2022-03-17

申请号：US17019479

申请日：2020-09-14

Applicant: Intel Corporation

Inventor： Sreenivas Kothandaraman ,  Karthik Vaidyanathan ,  Abhishek R. Appu ,  Karol Szerszen ,  Prasoonkumar Surti

IPC: G06T1/20 ,  G06F9/38 ,  G06T7/90 ,  G06F16/907

Abstract: An apparatus to facilitate compression of memory data is disclosed. The apparatus comprises one or more processors to receive uncompressed data, adapt a format of the uncompressed data to a compression format, perform a color transformation from a first color space to a second color space, perform a residual computation to generate residual data, compress the residual data via entropy encoding to generate compressed data and packing the compressed data.

公开(公告)号：US11263800B2

公开(公告)日：2022-03-01

申请号：US16728375

申请日：2019-12-27

Applicant: Intel Corporation

Inventor： Karol Szerszen ,  Prasoonkumar Surti ,  Gabor Liktor ,  Karthik Vaidyanathan ,  Sven Woop

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/08 ,  G06T1/20 ,  G06T17/10

Abstract: Apparatus and method for grouping rays based on quantized ray directions. For example, one embodiment of an apparatus comprises: An apparatus comprising: a ray generator to generate a plurality of rays; ray direction evaluation circuitry/logic to generate approximate ray direction data for each of the plurality of rays; ray sorting circuitry/logic to sort the rays into a plurality of ray queues based, at least in part, on the approximate ray direction data.

公开(公告)号：US11244479B2

公开(公告)日：2022-02-08

申请号：US16919839

申请日：2020-07-02

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Hugues Labbe ,  Atsuo Kuwahara ,  Sameer KP ,  Jonathan Kennedy ,  Murali Ramadoss ,  Michael Apodaca ,  Abhishek Venkatesh

IPC: G06T11/00 ,  G06T1/20 ,  G06T1/60 ,  G06T15/00

Abstract: Systems, apparatuses and methods may provide for technology that determines a stencil value and uses the stencil value to control, via a stencil buffer, a coarse pixel size of a graphics pipeline. Additionally, the stencil value may include a first range of bits defining a first dimension of the coarse pixel size and a second range of bits defining a second dimension of the coarse pixel size. In one example, the coarse pixel size is controlled for a plurality of pixels on a per pixel basis.

公开(公告)号：US11189076B2

公开(公告)日：2021-11-30

申请号：US16929671

申请日：2020-07-15

Applicant: INTEL CORPORATION

Inventor： Karthik Vaidyanathan ,  Sven Woop ,  Carsten Benthin

IPC: G06T15/06 ,  G06T1/60 ,  G06T9/40 ,  G06T17/00

Abstract: Apparatus and method for preventing re-traversal of a prior path on a restart. For example, one embodiment of an apparatus comprises: a ray generator to generate a plurality of rays in a graphics scene; a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes, wherein the BVH comprises a specified number of child nodes at a current BVH level beneath a parent node in the hierarchy; circuitry to traverse one or more of the rays through the BVH to form a current traversal path and intersect the one or more rays with primitives contained within the nodes, wherein the circuitry is to process entries from the top of a first data structure comprising entries each associated with a child node at the current BVH level, the entries being ordered from top to bottom based on a sorted distance of each respective child node.

公开(公告)号：US11030713B2

公开(公告)日：2021-06-08

申请号：US15483829

申请日：2017-04-10

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Prasoonkumar Surti ,  Michael Apodaca ,  Murali Ramadoss ,  Abhishek Venkatesh ,  Joydeep Ray ,  Abhishek R. Appu

IPC: G06T1/60 ,  G06T9/00 ,  H04N19/503 ,  H04N19/436

Abstract: An embodiment of a graphics apparatus may include an embedded local memory, and a memory extender communicatively coupled to the embedded local memory to extend the embedded local memory. The memory extender may be configured to compress information and store the compressed information in the embedded local memory. Additionally, or alternatively, the memory extender may be configured to expose the embedded local memory for non-local access. Other embodiments are disclosed and claimed.

公开(公告)号：US10957095B2

公开(公告)日：2021-03-23

申请号：US16056222

申请日：2018-08-06

Applicant: Intel Corporation

Inventor： Karthik Vaidyanathan ,  Won-Jong Lee ,  Gabor Liktor ,  John G. Gierach ,  Pawel Majewski ,  Prasoonkumar Surti ,  Carsten Benthin ,  Sven Woop ,  Thomas Raoux

IPC: G06T15/00 ,  G06T15/06 ,  G06T15/80 ,  G06T1/60 ,  G09G5/36

Abstract: Apparatus and method for programmable ray tracing with hardware acceleration on a graphics processor. For example, one embodiment of a graphics processor comprises shader execution circuitry to execute a plurality of programmable ray tracing shaders. The shader execution circuitry includes a plurality of single instruction multiple data (SIMD) execution units. Sorting circuitry regroups data associated with one or more of the programmable ray tracing shaders to increase occupancy for SIMD operations performed by the SIMD execution units; and fixed-function intersection circuitry coupled to the shader execution circuitry detects intersections between rays and bounding volume hierarchies (BVHs) and/or objects contained therein and to provide results indicating the intersections to the sorting circuitry.

公开(公告)号：US20200311041A1

公开(公告)日：2020-10-01

申请号：US16371342

申请日：2019-04-01

Applicant: Intel Corporation

Inventor： Prasoonkumar Surti ,  Abhishek R. Appu ,  Karol Szerszen ,  Eric Liskay ,  Karthik Vaidyanathan

IPC: G06F16/22 ,  G06N20/00 ,  G06T1/20

Abstract: Embodiments are generally directed to compression for compression for sparse data structures utilizing mode search approximation. An embodiment of an apparatus includes one or more processors including a graphics processor to process data; and a memory for storage of data, including compressed data. The one or more processors are to provide for compression of a data structure, including identification of a mode in the data structure, the data structure including a plurality of values and the mode being a most repeated value in a data structure, wherein identification of the mode includes application of a mode approximation operation, and encoding of an output vector to include the identified mode, a significance map to indicate locations at which the mode is present in the data structure, and remaining uncompressed data from the data structure.

公开(公告)号：US10665006B2

公开(公告)日：2020-05-26

申请号：US16023647

申请日：2018-06-29

Applicant: Intel Corporation

Inventor： Pradeep Ramani ,  Karthik Vaidyanathan ,  Prasoonkumar Surti

IPC: G06T15/00 ,  G06F9/38 ,  G06F9/48 ,  G06T1/20

Abstract: A mechanism is described for facilitating efficient prediction of most commonly occurring values in data blocks in computing environments. An apparatus of embodiments, as described herein, includes one or more processors to perform parallel calculations on values associated with multiple sub-blocks of a data block, and predict, based on the parallel calculations, a most commonly-occurring value in the data block. The apparatus if further to classify the most commonly-occurring value as a mode value for one or more data types to be used with one or more applications.