公开(公告)号：WO1990005993A1

公开(公告)日：1990-05-31

申请号：PCT/US1988004155

申请日：1988-11-21

Applicant: MICRON TECHNOLOGY, INC. ,  LEE, Ruojia, R.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/265

CPC classification number: H01L29/6659 ,  H01L21/26506 ,  H01L21/76202 ,  H01L21/76213 ,  H01L21/76216 ,  H01L29/167 ,  H01L29/78

Abstract: Implantation of germanium (45) into a PMOS buried channel to permit the enhancement implant profile (to 45) to be made more shallow. The shallow profile will reduce or eventually solve P-channel buried channel-induced short channel effects and enable further decrease in device length to deep sub-micron range. Benefits include better short channel characteristics, i.e., higher punch through voltage BVDSS, less VT sensitivity to the drain voltage (defined as curl) and better subthreshold leakage characteristics.

Abstract translation: 将锗（45）植入PMOS掩埋沟道以允许增强植入轮廓（至45）变得更浅。 浅剖面将减少或最终解决P沟道掩埋沟道引起的短沟道效应，并使器件长度进一步减小到深亚微米范围。 优点包括更好的短通道特性，即更高的穿通电压BVDSS，对漏极电压的VT灵敏度（定义为卷曲）以及更好的亚阈值泄漏特性。

公开(公告)号：WO1990001795A1

公开(公告)日：1990-02-22

申请号：PCT/US1988002726

申请日：1988-08-12

Applicant: MICRON TECHNOLOGY, INC. ,  MAXWELL, Clifford, A. ,  LOWREY, Tyler, A.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/283

CPC classification number: H01L27/10873 ,  H01L21/76889 ,  H01L29/665

Abstract: Salicidation of conductive levels in DRAM semiconductor devices is described. A poly I pattern is established, along with source drain implants. Oxide (25) is established along poly sidewalls in a manner which permits sidewall isolation. An isolating nitride (27) is formed, followed by a poly II pattern covered with another isolating nitride (37). An exposed sidewall of the poly II is oxidized to form oxide pattern (41). A refractory metal, such as titanium, is sputtered onto the top surface of the wafer and is sintered in a nitrogen atmosphere. TiSi2 is formed where the titanium is exposed to elemental silicon, while oxide patterns result in the titanium reacting only with the nitrogen. The titanium nitride and any unreacted titanium may then be selectively etched, leaving a desired pattern of TiSi2.

Abstract translation: 描述了DRAM半导体器件中导电水平的饱和度。 建立了poly I图案，以及源漏植入。 氧化物（25）以允许侧壁隔离的方式沿着多边形建立。 形成隔离氮化物（27），随后是被另一个隔离氮化物（37）覆盖的聚II图案。 聚II的暴露的侧壁被氧化以形成氧化物图案（41）。 将诸如钛的难熔金属溅射到晶片的顶表面上并在氮气气氛中烧结。 形成TiSi2，其中钛暴露于元素硅，而氧化物图形导致钛仅与氮反应。 然后可以选择性地蚀刻氮化钛和任何未反应的钛，留下所需的TiSi 2图案。

公开(公告)号：WO1989011733A1

公开(公告)日：1989-11-30

申请号：PCT/US1988001760

申请日：1988-05-24

Applicant: MICRON TECHNOLOGY, INC. ,  TONG, Paul, Chak, Foon ,  LOWREY, Tyler, A. ,  PARKINSON, Ward, D.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01L21/283

CPC classification number: H01L21/76895 ,  H01L21/28518 ,  H01L21/76879

Abstract: Low resistivity interconnects and silicided N+/P+ active area are formed by sputtering a blanket layer of titanium (33) onto a wafer surface (13) which has the interconnection pattern defined by a thin polysilicon layer (29). A thin oxide layer (27) underneath the polysilicon interconnection pattern serves as an etch stop in the local interconnect photo/etch step. This unprotected oxide layer remaining on top of the N+/P+ active area will be removed by a wet etch prior to the sputtering step. Titanium is then reacted with the polysilicon to form TiSi2, and unreacted titanium and TiN are removed. A subsequent metallization layer acts as an alpha radiation shield and as a capacitive ground.

Abstract translation: 通过将钛（33）的覆盖层溅射到由薄多晶硅层（29）限定的互连图案的晶片表面（13）上形成低电阻率互连和硅化N + / P +有源区。 在多晶硅互连图案下方的薄氧化物层（27）用作局部互连光刻/蚀刻步骤中的蚀刻停止。 残留在N + / P +有效面积顶部的未保护的氧化物层将在溅射步骤之前通过湿式蚀刻去除。 然后使钛与多晶硅反应形成TiSi 2，并除去未反应的钛和TiN。 随后的金属化层用作α辐射屏蔽和作为电容地。

公开(公告)号：WO1998031100A1

公开(公告)日：1998-07-16

申请号：PCT/US1997022767

申请日：1997-12-16

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  SCHICHT, Steve

IPC: H03K19/0185

CPC classification number: G11C11/4091

Abstract: An input/output device for use with an array of memory cells (12) having a digitline (BL) and a complement of the digitline (BL*) running through the array is fabricated on a substrate (58) having active areas formed therein. Sensing transistors (40, 40') have terminals fabricated in the active areas which are responsive to the digitline (BL) and the complement of the digitline (BL*) for sensing signals thereon in a read operation. Switching transistors (24, 24') have terminals fabricated in the active areas which are responsive to the sensing transistors for selectively conducting the signals sensed by the sensing transistors. Certain terminals of the sensing transistors (40, 40') and certain terminals of the switching transistors (24, 24') are fabricated in the same active area.

Abstract translation: 在具有形成在其中的有效区域的基板（58）上制造用于与具有数字线（BL）和数字线（BL *）的互补的阵列的存储单元阵列一起使用的输入/输出装置。 感测晶体管（40,40'）具有制造在有效区域中的终端，其响应于数字线（BL）和数字线（BL *）的补码，用于在读取操作中感测信号。 开关晶体管（24,24'）具有制造在有源区域中的端子，其响应于感测晶体管，用于选择性地传导由感测晶体管感测的信号。 感测晶体管（40,40'）的某些端子和开关晶体管（24,24'）的某些端子被制造在相同的有源区域中。

公开(公告)号：WO1998031039A3

公开(公告)日：1998-07-16

申请号：PCT/US1997024281

申请日：1997-12-31

Applicant: MICRON TECHNOLOGY, INC. ,  CATHEY, David, A. ,  WATKINS, Charles, M. ,  HOFMANN, James, J.

Inventor： MICRON TECHNOLOGY, INC.

IPC: H01J29/89

公开(公告)号：WO1998019307A1

公开(公告)日：1998-05-07

申请号：PCT/US1997019580

申请日：1997-10-28

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  KEETH, Brent

IPC: G11C07/00

CPC classification number: G11C7/1093 ,  G11C7/1042 ,  G11C7/1078 ,  G11C7/22

Abstract: A data bus is described which has integrated circuits, such as memory circuits, coupled thereto. The integrated circuits include an input buffer circuit adapted to receive and latch high speed data transmissions. The input buffer circuit equilibrates a sensing circuit, samples input data, senses the sampled input data, and latches the sensed data during different phases of an input clock cycle. An input buffer circuit is described which has two receiver circuits for receiving data transmissions having higher speed data transmissions.

Abstract translation: 描述了具有集成电路的数据总线，诸如与其耦合的存储器电路。 集成电路包括适于接收和锁存高速数据传输的输入缓冲器电路。 输入缓冲电路平衡感测电路，采样输入数据，感测采样输入数据，并在输入时钟周期的不同阶段锁存感测数据。 描述了一种输入缓冲器电路，其具有用于接收具有较高速度数据传输的数据传输的两个接收器电路。

公开(公告)号：WO1998015958A1

公开(公告)日：1998-04-16

申请号：PCT/US1997018063

申请日：1997-10-07

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  MARTIN, Chris, G. ,  CASPER, Stephen, L.

IPC: G11C07/06

CPC classification number: G11C17/18 ,  G11C7/06

Abstract: A detection circuit for detecting unblown and blown conditions for an anti-fuse. The detection circuit includes a precharge circuit for applying a precharge to the anti-fuse during a precharge time interval, and a sampling circuit for coupling the anti-fuse to the detection node to provide a voltage at the detection node that is indicative of the ability of the anti-fuse to retain a charge during the discharge time interval. An output circuit that is coupled to the detection node is responsive to the voltage provided at the detection node to provide a first output for indicating an unblown condition for the anti-fuse and a second output for indicating a blown condition for the anti-fuse.

Abstract translation: 一种用于检测用于反熔丝的未吹制和吹制条件的检测电路。 检测电路包括预充电电路，用于在预充电时间间隔期间向反熔丝施加预充电;以及采样电路，用于将反熔丝耦合到检测节点，以在检测节点处提供指示能力的电压 的反熔丝在放电时间间隔期间保持电荷。 耦合到检测节点的输出电路响应于在检测节点处提供的电压，以提供用于指示用于反熔丝的未吹扫状态的第一输出和用于指示用于反熔丝的吹出状态的第二输出。

公开(公告)号：WO1997028605A1

公开(公告)日：1997-08-07

申请号：PCT/US1997000948

申请日：1997-01-30

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  WRIGHT, Jeffrey, P. ,  ZHENG, Hua

IPC: H03K21/00

CPC classification number: H03K21/00

Abstract: A shared counter (32) performs multiple counting functions in an electronic circuit, such as a memory integrated circuit. An input selection circuit (21) selects one of M input data sets at a given time to be provided as counter initialization data. A counter circuit (32) provides counter output data based on the counter initialization data. An output circuit (35) provides the counter output data to K destination circuits in the electronic circuit. The output circuit (35) provides only one of the K destination circuits with the counter output data at a given time.

Abstract translation: 共享计数器（32）在诸如存储器集成电路的电子电路中执行多个计数功能。 输入选择电路（21）在给定时间选择M个输入数据组中的一个作为计数器初始化数据提供。 计数器电路（32）基于计数器初始化数据提供计数器输出数据。 输出电路（35）将计数器输出数据提供给电子电路中的K个目标电路。 在给定时间，输出电路（35）仅提供K个目标电路中的一个与计数器输出数据。

公开(公告)号：WO1997028564A1

公开(公告)日：1997-08-07

申请号：PCT/US1997001786

申请日：1997-01-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  ROBERTS, Ceredig ,  SRINIVASAN, Anand ,  SANDHU, Gurtej ,  SHARAN, Sujit

IPC: H01L21/768

CPC classification number: H01L21/76865 ,  H01L21/76843 ,  H01L21/76844 ,  H01L21/76862 ,  H01L21/76877 ,  H01L23/485 ,  H01L23/53223 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Disclosed is a method for providing improved step coverage of contacts with conductive materials, and particularly metals. A conductive layer (14) is deposited over an insulating layer, either before or after contact opening (20) formation. After both conductive layer deposition and contact formation, a facet etch is performed to slope the conductive layer (14) overlying the contact lip (27) while depositing material from the conductive layer (14) into the lower corner (30) of the contact (20), where coverage has traditionally been poor. A second conductive layer (40) may then be deposited into the contact to supplement coverage provided by the first conductive layer (14) and the facet etch.

Abstract translation: 公开了一种用于提供与导电材料，特别是金属的接触的改进的台阶覆盖的方法。 导电层（14）在接触开口（20）形成之前或之后沉积在绝缘层上。 在导电层沉积和接触形成两者之后，执行小面蚀刻以使覆盖接触唇缘（27）的导电层（14）倾斜，同时将材料从导电层（14）沉积到触点的下角（30） 20），其覆盖率一直很差。 然后可以将第二导电层（40）沉积到触点中以补充由第一导电层（14）提供的覆盖面和小面蚀刻。

公开(公告)号：WO1997028561A1

公开(公告)日：1997-08-07

申请号：PCT/US1996010196

申请日：1996-06-12

Applicant: MICRON TECHNOLOGY, INC.

Inventor： MICRON TECHNOLOGY, INC. ,  IYER, Ravi ,  THAKUR, Randhir, P., S. ,  RHODES, Howard, E.

IPC: H01L21/316

CPC classification number: H01L21/02164 ,  H01L21/02129 ,  H01L21/02271 ,  H01L21/31612 ,  H01L21/31625

Abstract: The fixed charge in a borophosphosilicate glass insulating film deposited on a semiconductor device is reduced by reacting an organic precursor such as TEOS with O3. When done at temperatures higher than approximately 480 degrees C, the carbon level in the resulting film appears to be reduced, resulting in a higher threshold voltage for field transistor devices.

Abstract translation: 通过使诸如TEOS的有机前体与O 3反应，沉积在半导体器件上的硼磷硅玻璃绝缘膜中的固定电荷被还原。 当在高于约480摄氏度的温度下完成时，所得膜中的碳水平似乎降低，导致场效应晶体管器件的阈值电压更高。