公开(公告)号：US20210191617A1

公开(公告)日：2021-06-24

申请号：US16800221

申请日：2020-02-25

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu ,  Bruce A. Liikanen ,  Peter Feeley ,  Larry J. Koudele ,  Shane Nowell ,  Steven Michael Kientz

IPC: G06F3/06 ,  G06F12/10 ,  G11C16/26

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to initialize a block family associated with a memory device; initialize a timeout associated with the block family; initializing a low temperature and a high temperature using a reference temperature at the memory device; responsive to programming a block residing on the memory device, associate the block with the block family; and responsive to at least one of: detecting expiration of the timeout or determining that a difference between the high temperature and the low temperature is greater than or equal to a specified threshold temperature value, close the block family.

公开(公告)号：US20200348881A1

公开(公告)日：2020-11-05

申请号：US16930064

申请日：2020-07-15

Applicant: Micron Technology, Inc.

Inventor： Mustafa N Kaynak ,  Sampath K. Ratnam ,  Zixiang Loh ,  Nagendra Prasad Ganesh Rao ,  Larry K. Koudele ,  Vamsi Pavan Rayaprolu ,  Patrick R. Khayat ,  Shane Nowell

IPC: G06F3/06 ,  G06F11/07

Abstract: A processing device, operatively coupled with a memory device, is configured to identify a temperature related to a memory device of a plurality of memory devices; to determine, whether the temperature satisfies a threshold temperature condition; responsive to detecting that the temperature related to the memory device satisfies the threshold temperature condition, to identify an entry associated with the memory device from a plurality of entries in a data structure, wherein each entry of the plurality of entries corresponds to one of the plurality of memory devices; to determine a parameter value associated with the memory device from the entry, wherein the parameter value is for a programming operation to store data at the memory device; to adjust the parameter value associated with the memory device to generate an adjusted parameter value; and to store the adjusted parameter value in the entry of the data structure.

公开(公告)号：US20200152280A1

公开(公告)日：2020-05-14

申请号：US16741198

申请日：2020-01-13

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish R. Singidi ,  Shane Nowell ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam

IPC: G11C16/34 ,  G06F11/10 ,  G06F11/30 ,  G11C29/42 ,  G11C29/52 ,  G11C16/26

Abstract: A processing device in a memory system determines that a first metric of a first memory unit on a first plane of a memory device satisfies a first threshold criterion. The processing device further determines whether a second metric of a second memory unit on a second plane of the memory device satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second metric satisfying the second threshold criterion, the processing device performs a multi-plane data integrity operation to determine a first reliability statistic for the first memory unit and a second reliability statistic for the second memory unit in parallel.

公开(公告)号：US10553290B1

公开(公告)日：2020-02-04

申请号：US16175657

申请日：2018-10-30

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Harish R. Singidi ,  Shane Nowell ,  Vamsi Pavan Rayaprolu ,  Sampath K. Ratnam

IPC: G11C16/26 ,  G11C16/34 ,  G11C29/52 ,  G11C29/42 ,  G06F11/30 ,  G06F11/10

Abstract: A processing device in a memory system determines that a first read count of a first data block on a first plane of a memory component satisfies a first threshold criterion. The processing device further determines whether a second read count of a second data block on a second plane of the memory component satisfies a second threshold criterion, wherein the second block is associated with the first block, and wherein the second threshold criterion is lower than the first threshold criterion. Responsive to the second read count satisfying the second threshold criterion, the processing device performs a multi-plane scan to determine a first error rate for the first data block and a second error rate for the second data block in parallel.

公开(公告)号：US10403378B1

公开(公告)日：2019-09-03

申请号：US15991822

申请日：2018-05-29

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Peter Feeley ,  Kishore Kumar Muchherla ,  Renato C. Padilla ,  Shane Nowell

IPC: G11C11/34 ,  G11C16/34 ,  G11C7/04 ,  G11C7/22 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

Abstract: A temperature associated with the memory component is determined. A frequency to perform an operation on a memory cell associated with the memory component is determined based on the temperature associated with the memory component. The operation is performed on the memory cell at the determined frequency to transition the memory cell from a state associated with an increased error rate for data stored at the memory cell to another state associated with a decreased error rate for the data stored at the memory cell.

公开(公告)号：US20190250843A1

公开(公告)日：2019-08-15

申请号：US16100681

申请日：2018-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Sampath K. Ratnam ,  Vamsi Pavan Rayaprolu ,  Mustafa N. Kaynak ,  Sivagnanam Parthasarathy ,  Kishore Kumar Muchherla ,  Shane Nowell ,  Peter Feeley ,  Qisong Lin

IPC: G06F3/06 ,  G06F11/10 ,  G11C29/52

CPC classification number: G06F3/0647 ,  G06F3/0619 ,  G06F3/0673 ,  G06F11/1068 ,  G11C29/52

Abstract: At least one data of a set of data stored at a memory cell of a memory component is determined to be associated with an unsuccessful error correction operation. A determination is made as to whether a programming operation associated with the set of data stored at the memory cell has completed. The at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation is recovered in response to determining that the programming operation has completed. Another memory cell of the memory component is identified in response to recovering the at least one data of the set of data stored at the memory cell that is associated with the unsuccessful error correction operation. The set of data including the recovered at least one data is provided to the other memory cell of the memory component.

公开(公告)号：US11853556B2

公开(公告)日：2023-12-26

申请号：US17832842

申请日：2022-06-06

Applicant: Micron Technology, Inc.

Inventor： Steven Michael Kientz ,  Larry J. Koudele ,  Shane Nowell ,  Michael Sheperek ,  Bruce A. Liikanen

IPC: G06F3/06 ,  G06F11/30

CPC classification number: G06F3/0614 ,  G06F3/064 ,  G06F3/0631 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/3037 ,  G06F11/3058

Abstract: A system including a memory device and a processing device, the processing device to identify a first temperature level of a first set of memory blocks associated with the memory device, and a second temperature level of a second set of memory blocks associated with the memory device, and determine that a condition is satisfied based on a comparison of the first temperature level, the second temperature level, and an adjustable threshold level. In response to the condition being satisfied, the processing device is to combine the first set of memory blocks and the second set of memory blocks to generate a combined set of memory blocks.

公开(公告)号：US20230325273A1

公开(公告)日：2023-10-12

申请号：US18207525

申请日：2023-06-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Sampath K. Ratnam ,  Peter Feeley ,  Sivagnanam Parthasarathy ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F11/07

CPC classification number: G06F11/0793 ,  G06F11/0751 ,  G06F11/0727

Abstract: Systems and methods are disclosed including a memory device and a processing device operatively coupled to the memory device. The processing device can perform operations including detecting a read error with respect to data residing in a first block of the memory device, wherein the first block is associated with a voltage offset bin; determining a most recently performed error-handling operation performed on a second block associated with the voltage offset bin; and performing the error-handling to recover the data.

公开(公告)号：US11783901B2

公开(公告)日：2023-10-10

申请号：US17880980

申请日：2022-08-04

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Shane Nowell ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Jiangang Wu ,  Devin M. Batutis ,  Xiangang Luo

IPC: G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  G06F11/07 ,  G11C16/04

CPC classification number: G11C16/34 ,  G06F3/0604 ,  G06F3/0632 ,  G06F3/0659 ,  G06F3/0679 ,  G06F11/076 ,  G06F11/0727 ,  G06F11/0793 ,  G11C16/26 ,  G11C16/0483

Abstract: A system includes a memory device and a processing device. The processing device performs, at a first frequency, a first scan of a page of a block family that measures a first data state metric and identifies a specific bin corresponding to a measured value for the first data state metric. Processing device updates a bin, to which the page is assigned, to match the specific bin. Processing device performs, at a second frequency higher than the first frequency, a second scan of the page to measure a second data state metric for read operations performed using a threshold voltage offset value from each of multiple bins. Processing device updates the bin, to which the page is assigned for the specified die, to match a second bin having the threshold voltage offset value that yields a lowest read bit error rate from the second scan.

公开(公告)号：US11676664B2

公开(公告)日：2023-06-13

申请号：US17883538

申请日：2022-08-08

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Sampath K. Ratnam ,  Shane Nowell ,  Sivagnanam Parthasarathy ,  Mustafa N. Kaynak ,  Karl D. Schuh ,  Peter Feeley ,  Jiangang Wu

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/20 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

CPC classification number: G11C16/102 ,  G11C16/20 ,  G11C16/26 ,  G11C16/30 ,  G11C16/32 ,  G11C16/3495

Abstract: A processing device of a memory sub-system is configured to detect a power on event that is associated with a memory device and indicates that power has been restored to the memory device; estimate a duration of a power off state preceding the power on event associated with the memory device; and update voltage bin assignments of a plurality of blocks associated with the memory device based on the duration of the power off state.