公开(公告)号：AT214193T

公开(公告)日：2002-03-15

申请号：AT98930199

申请日：1998-06-12

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C11/407 ,  G11C7/10 ,  G11C11/401 ,  G11C7/00 ,  G11C5/06

Abstract: A command buffer for use in packetized DRAM includes a two stage shift register for shifting or sequentially storing two of four 10-bit command words in each packet. After the first two words of each packet have been stored, they are transferred to a first storage register and output from the first storage register. After the final two words of each packet have been shifted into the shift register, they are transferred to a second storage register and output from the second storage register. The first two command words are output from the first storage register before the last two command words are applied to the command buffer. As a result, the DRAM can start processing the first two command words of the command packet before the entire command packet has been received.

公开(公告)号：AU9571698A

公开(公告)日：1999-04-05

申请号：AU9571698

申请日：1998-09-18

Applicant: MICRON TECHNOLOGY INC

Inventor： KEETH BRENT ,  MANNING TROY A

IPC: G06F1/10 ,  G11C7/22 ,  H03K5/13 ,  H03L7/07 ,  H03L7/081 ,  G11C7/00

Abstract: A variable delay circuit is formed by a fine delay circuit and a coarse delay circuit. The fine delay circuit adjusts the delay of a delayed clock signal in relatively small phase increments with respect to an input clock signal. The coarse delay circuit adjusts the timing of a digital signal in relatively large phase increments. The delayed clock signal is used to clock a register to which the digital signal is applied to control the timing a the digital signal clocked through the register responsive to adjusting the timing of the fine delay circuit and the coarse delay circuit. The timing relationship is initially adjusted by altering the delay of the fine delay circuit. Whenever the maximum or minimum delay of the fine delay circuit is reached, the coarse delay circuit is adjusted. The variable delay circuit may be used in a memory device to control the timing at which read data is applied to the data bus of the memory device. The fine delay circuit includes a multi-tapped delay line coupled to a multiplexer that selects one of the taps for use in generating the delayed clock. When the first or last tap is selected, the timing of the coarse delay circuit is adjusted. The coarse delay circuit includes a counter that generates the digital signal upon counting from an initial count to the terminal count. The coarse delay circuit is adjusted by adjusting the initial count of the counter.

公开(公告)号：AU9292698A

公开(公告)日：1999-02-16

申请号：AU9292698

申请日：1998-07-20

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A ,  MARTIN CHRIS G

IPC: G11C7/06

Abstract: A sense amplifier that amplifies data signals in either a normal mode or an altered mode. In the normal mode, the data signals must be complementary of each other while in the altered mode, the data signals may, but need not be, complementary of each other. The sense amplifier includes two sense amplifier stages, the first of which drives the second, and each sense amplifier stage includes two identical sense amplifier circuits. A first input of each sense amplifier in the first stage receives a respective data signal, and a first input of each sense amplifier in the second stage receives an output signal from a respective sense amplifier in the first stage. In the normal mode, a mode control circuit couples each of the other data signals to a respective second input of each sense amplifier in the first stage so that the sense amplifiers receive both of the complimentary data signals at their differential inputs. In the altered mode, the mode control circuit couples a reference voltage to the second inputs of the sense amplifiers in the first stage so that the sense amplifiers compare a respective data signal to the reference voltage. The mode control circuit also alters the operation of the second stage. In the normal mode, the mode control circuit couples an output signal from the other sense amplifier in the first stage to a respective second input of each sense amplifier in the second stage so that the sense amplifiers receive at their differential inputs both of the complimentary output signals from each sense amplifier in the first stage. In the altered mode, the mode control circuit couples a data signal to the respective second input of each sense amplifier in the second stage so that the sense amplifiers compare an output signal from a respective sense amplifier in the first stage to a respective data signal.

公开(公告)号：AU7980898A

公开(公告)日：1999-01-04

申请号：AU7980898

申请日：1998-06-18

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C11/407 ,  G11C5/06 ,  G11C7/10 ,  G11C7/22

Abstract: A computer system with a memory device having plural memory banks and a method of accessing a selected one of the memory banks, the memory device includes local control signal generators that control timing of operations in each respective block of a memory array. Overall timing of the device is controlled by first and second global control signals generated in a command sequencer and decoder. The second global control signal is derived from a delayed version of the first signal, and both signals are applied to local control signal generators along with address bits indicating a selected block. Local timing is determined by the global control signals and by local circuitry within the local control signal generators.

公开(公告)号：AU6543398A

公开(公告)日：1998-09-22

申请号：AU6543398

申请日：1998-03-05

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/00 ,  G11C7/22 ,  H03K5/13 ,  H03L7/081

Abstract: A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.

公开(公告)号：AU6269998A

公开(公告)日：1998-08-26

申请号：AU6269998

申请日：1998-02-11

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C11/407 ,  G06F1/10 ,  H03K5/13 ,  H03L7/093 ,  H03L7/099 ,  H03L7/06 ,  H03K5/135

Abstract: A clock generator circuit for an integrated circuit includes a phase detector comparing the phase of a delayed external clock signal to the phase of an internal clock signal. An error signal corresponding to the difference in phase between the two clock signals is applied to a differential amplifier where the error signal is offset by a value corresponding to the delay of an external clock signal as it is coupled to the phase detector. The offset error signal is applied to a control input of a voltage controlled oscillator which generates the internal clock signal. The phase of the internal clock signal it thus adjusted so that it is substantially the same as the phase of the external clock signal before being delayed as it is coupled to the phase detector and other circuitry in the integrated circuit. The voltage controlled oscillator is constructed to operate in a plurality of discrete frequency bands so that the offset error signal need only control the frequency of the internal clock signal over a relatively small range. The frequency band is selected by a signal from a register that is programmed by a user with data identifying the frequency of the external clock signal.

公开(公告)号：AU6863996A

公开(公告)日：1997-03-19

申请号：AU6863996

申请日：1996-08-28

Applicant: MICRON TECHNOLOGY INC

Inventor： CLOUD EUGENE H ,  WILLIAMS BRETT L ,  MANNING TROY A

IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/4076 ,  G11C11/409 ,  G11C11/407

Abstract: A memory circuit is described which has an output data strobe signal that indicates when valid data is available on the output lines. Several alternate signals and circuits are described which can be used for the output strobe signal. An echo clock signal is described which selectively follows an input clock signal in a synchronous memory system and indicated when valid output data is available. The output strobe signal is used to speed the reading of data from the output line by allowing a microprocessor, or other external circuit, to read the data from the output lines as soon as it is valid, thereby eliminating the need to wait a specified period of time.

公开(公告)号：WO2015187771A3

公开(公告)日：2017-05-04

申请号：PCT/US2015033889

申请日：2015-06-03

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G11C7/06 ,  G11C7/10

CPC classification number: G11C11/4091 ,  G11C7/065 ,  G11C7/1006 ,  G11C7/1012 ,  G11C11/4087 ,  G11C11/4093 ,  G11C11/4096 ,  G11C29/42

Abstract: The present disclosure includes apparatuses and methods related to determining an XOR value in memory. An example method can include performing a NAND operation on a data value stored in a first memory cell and a data value stored in a second memory cell. The method can include performing an OR operation on the data values stored in the first and second memory cells. The method can include performing an AND operation on the result of the NAND operation and a result of the OR operation without transferring data from the memory array via an input/output (I/O) line.

Abstract translation: 本公开包括与确定存储器中的异或值有关的设备和方法。 示例方法可以包括对存储在第一存储器单元中的数据值和存储在第二存储器单元中的数据值执行NAND操作。 该方法可以包括对存储在第一和第二存储器单元中的数据值执行或运算。 该方法可以包括对NAND操作的结果和OR操作的结果执行AND操作，而不通过输入/输出（I / O）线传输来自存储器阵列的数据。

公开(公告)号：US6393378B2

公开(公告)日：2002-05-21

申请号：US76453501

申请日：2001-01-16

Applicant: MICRON TECHNOLOGY INC

Inventor： MANNING TROY A

IPC: G06F11/22 ,  G06F11/00 ,  G11C11/401 ,  G11C29/44 ,  G11C29/50 ,  H01L21/82 ,  G06F11/30

CPC classification number: G06F11/006 ,  G11C29/44 ,  G11C29/50

Abstract: A method and circuit for recording the performance parameters in an integrated circuit. A speed grade register is programmed by the manufacturer with an indication of the speed capability of the integrated circuit. The integrated circuit also includes a clock speed register that is programmed by the user with an indication of the frequency of a clock signal that will be used to synchronize the operation of the integrated circuit. The speed grade and clock speed indications are used to select a set of performance data from a performance data register to provide an indication of the performance of the integrated circuit at the indicated speed grade and clock speed.

Abstract translation: 一种用于在集成电路中记录性能参数的方法和电路。 制造商对速度等级寄存器进行编程，并指示集成电路的速度能力。 该集成电路还包括时钟速度寄存器，该时钟速度寄存器由用户编程，其具有用于同步集成电路的操作的时钟信号的频率的指示。 速度等级和时钟速度指示用于从性能数据寄存器中选择一组性能数据，以指定的速度等级和时钟速度提供集成电路的性能指示。

公开(公告)号：WO2012094481A3

公开(公告)日：2012-09-20

申请号：PCT/US2012020312

申请日：2012-01-05

Applicant: MICRON TECHNOLOGY INC ,  MANNING TROY A ,  CULLEY MARTIN L ,  LARSEN TROY D

Inventor： MANNING TROY A ,  CULLEY MARTIN L ,  LARSEN TROY D

IPC: G06F12/06 ,  G06F12/10

CPC classification number: G06F12/1045 ,  G06F12/0246 ,  G06F12/0292 ,  G06F12/1009 ,  G06F12/1027 ,  G06F2212/1004 ,  G06F2212/7201 ,  Y02B60/1225 ,  Y02D10/13

Abstract: The present disclosure includes devices, systems, and methods for memory address translation. One or more embodiments include a memory array and a controller coupled to the array. The array includes a first table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a data segment stored in the array and a logical address. The controller includes a second table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the first table and a logical address. The controller also includes a third table having a number of records, wherein each record includes a number of entries, wherein each entry includes a physical address corresponding to a record in the second table and a logical address.

Abstract translation: 本公开包括用于存储器地址转换的装置，系统和方法。 一个或多个实施例包括存储器阵列和耦合到阵列的控制器。 阵列包括具有多个记录的第一表，其中每个记录包括多个条目，其中每个条目包括对应于阵列中存储的数据段的物理地址和逻辑地址。 控制器包括具有多个记录的第二表，其中每个记录包括多个条目，其中每个条目包括对应于第一表中的记录的物理地址和逻辑地址。 控制器还包括具有多个记录的第三表，其中每个记录包括多个条目，其中每个条目包括对应于第二表中的记录的物理地址和逻辑地址。