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公开(公告)号：GB2269284B
公开(公告)日：1995-08-09
申请号：GB9316175
申请日：1992-10-13
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
IPC: H03D3/00 , H04L7/033 , H04L27/233 , H03D3/18
Abstract: This patent application discusses a direct phase digitizing apparatus (303) for use in a radiotelephone (101). The direct phase digitizing apparatus (303) accepts a first analog signal (309) having a phase, a voltage range and a first frequency. First, the direct phase digitizer generates an estimated phase map (611) having a second frequency and N-bits of resolution. Second, the direct phase digitizer detects a predetermined-voltage crossing (409) of the first analog signal (309). Third, using the predetermined-voltage crossings, the direct phase digitizer samples the estimated phase map. Fourth, a digital phase signal (623) is generated using the samples of the estimated phase map.
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公开(公告)号：GB2273406A
公开(公告)日：1994-06-15
申请号：GB9322408
申请日：1993-01-21
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
Abstract: The present disclosure includes a discussion of a method of phase adjustment for use in a clock recovery scheme. The phase adjustment circuit automatically holds the clock phase during periods of poor channel quality. The clock recovery scheme generates a sampling clock signal (139) which is synchronous with the received signal (131). Additionally, the clock recovery scheme generates at least two error signals (347, 349, 351, 353) which indicate the quality of the received signal at different sampling phases. The smallest error signal is referred to as the minimum error value. Each error signal (347, 349, 351, 353) is compared to the minimum error value, creating a corresponding normalized error magnitude signal. Each normalized error magnitude signal is processed to determine the desired phase of the sampling clock signal. Dependent upon the processing of the normalized error magnitude signals, the phase of the sampling clock signal is either shifted or maintained until the next sampling point.
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公开(公告)号：CZ9302562A3
公开(公告)日：1994-05-18
申请号：CZ256293
申请日：1993-01-25
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
IPC: H04Q7/38 , H04J3/00 , H04L7/02 , H04L7/033 , H04L7/04 , H04L7/08 , H04L7/10 , H04L27/22 , H04L7/00 , H03D3/24
CPC classification number: H04L7/0062 , H04L7/0337 , H04L7/042 , H04L7/10
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公开(公告)号：BR9205617A
公开(公告)日：1994-05-03
申请号：BR9205617
申请日：1992-09-21
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
IPC: H04L27/233 , A61F13/15 , H03D7/00 , H03D13/00 , H04L27/22
Abstract: The present patent application discusses a frequency translation apparatus for altering the effective frequency of the phase information of an input signal (115). The input signal (115) has a first phase ((theta)(t)) and a first frequency (fi). The phase of the input signal is extracted and digitized at a second frequency (fo), forming a second N-bit digital phase signal ((theta)'(t))(311). The frequency translation apparatus generates a third digital phase signal (319) which approximates the difference between (theta)(t) and (theta)'(t). Then, the frequency translation apparatus combines the second digital phase signal and the third digital phase signal, forming a fourth digital phase signal (307) substantially approximating the first phase signal.
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45.发明专利
公开(公告)号：CZ9302564A3
公开(公告)日：1994-03-16
申请号：CZ256493
申请日：1993-01-21
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
CPC classification number: H04L7/0062 , H04L7/0083
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Patent Agency Ranking
公开(公告)号：FI935259A0
公开(公告)日：1993-11-26
申请号：FI935259
申请日：1993-11-26
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
Abstract: The present disclosure includes a discussion of a decision-directed clock recovery system which includes circuitry to prevent false-locking and accelerate acquisition on a known symbol patterns. The clock recovery system has at least two control circuits. Each control circuit has an effective bandwidth and also generates a clock signal. The clock recovery system samples the received data signal using the two clock signals, forming a corresponding first and second sampled signal. The sampled signals are used to generate corresponding symbol decisions. The symbol decision signals are processed to detect a known symbol pattern in the received data signal. Upon detection of the known bit sequence, the characteristics of the clock recovery system are modified, namely, the effective bandwidth of the control circuits are modified.
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公开(公告)号：CA2102406A1
公开(公告)日：1993-09-27
申请号：CA2102406
申请日：1993-01-21
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J , BAKER JAMES C
Abstract: The method of synchronizing a sampling clock signal to a received data signal, the clock recovery circuit generates several clock signals at the symbol rate, with each clock signal having a unique phase. To permit fast initial acquisition, the set of clock signals includes a pair of clocks which differ in phase by one-half of a symbol interval. Additionally, the clock recovery circuitry generates error signals representing the difference between the phase of the received data signal and the phase of each clock signal. The error signals are processed over multiple symbol times to determine the optimal sampling phase. The clock recovery circuit then adjusts or maintains the phase of the symbol clock to provide the optimal sampling phase.
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公开(公告)号：CA2102108A1
公开(公告)日：1993-09-27
申请号：CA2102108
申请日：1993-01-21
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
Abstract: A method of and apparatus for compensating a received signal's phase compensates for the distortion caused by the asymmetrical characteristics of a voltage limiter. This compensation allows the received signal to be sampled at the positive and negative zero-crossings reducing the requirements of a local oscillator in a radiotelephone system. First, the phase of the received signal is sampled at the positive and negative zero-crossings, forming a corresponding positive-crossing and a negative-crossing phase value for the received signal. Second, the negative-crossing and positive-crossing phase values are combined, forming a first difference signal. Third, an estimated error signal is formed using the first difference signal. Fourth, the estimated error signal is combined with the positive or negative zero-crossing phase signals, substantially eliminating the asymmetrical distortion.
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公开(公告)号：FI932245A0
公开(公告)日：1993-05-18
申请号：FI932245
申请日：1993-05-18
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
Abstract: A phase combining method and apparatus for use in a diversity reception radiotelephone is described. The phase combining method and apparatus is a hybrid diversity technique which combines elements of maximal ratio combining (MRC) and level comparison selection diversity, which results in a simple and effective implementation of a diversity receiver with superior performance. The diversity receiver demodulates the received signals, extracts the phase, forming two phase signals. Then, the two phase signals are combined to form a third phase signal. One of the three phase signals is selected to be used for interpretation of a symbol in the Quadrature Phase Shift Keying (QPSK) constellation. The selection process is based on the received signal strength of the received signals.
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公开(公告)号：FI932245A
公开(公告)日：1993-05-18
申请号：FI932245
申请日：1993-05-18
Applicant: MOTOROLA INC
Inventor： LAROSA CHRISTOPHER P , CARNEY MICHAEL J
Abstract: A phase combining method and apparatus for use in a diversity reception radiotelephone is described. The phase combining method and apparatus is a hybrid diversity technique which combines elements of maximal ratio combining (MRC) and level comparison selection diversity, which results in a simple and effective implementation of a diversity receiver with superior performance. The diversity receiver demodulates the received signals, extracts the phase, forming two phase signals. Then, the two phase signals are combined to form a third phase signal. One of the three phase signals is selected to be used for interpretation of a symbol in the Quadrature Phase Shift Keying (QPSK) constellation. The selection process is based on the received signal strength of the received signals.
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