公开(公告)号：WO1994018775A1

公开(公告)日：1994-08-18

申请号：PCT/US1994001547

申请日：1994-02-10

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  STENGEL, Robert, E. ,  BACKOFF, Charles, A.

IPC: H04L27/36

CPC classification number: H04L27/362 ,  H03F3/2176 ,  H03F3/602

Abstract: A high efficiency amplitude/phase modulation amplifier circuit (100) includes a first (102) and a second (106) high efficiency amplifier. These amplifiers (102 and 106) amplify two constant amplitude/phase modulated signals. A combiner (104) combines the output signals from the amplifiers (102 and 106) to produce a combined signal to a load (108). Two shunt elements (202 and 204) are included to prevent the reactive components of the combined signal from reaching the amplifiers (102 and 106). With no reactive components reflected back, the amplifiers (102 and 106) can remain non-linear even though they are used to amplify an amplitude/phase modulated signal which includes Amplitude Modulation (AM) components.

Abstract translation: 高效率幅度/相位调制放大器电路（100）包括第一（102）和第二（106）高效放大器。 这些放大器（102和106）放大两个恒定幅度/相位调制信号。 组合器（104）组合来自放大器（102和106）的输出信号以产生与负载（108）的组合信号。 包括两个并联元件（202和204）以防止组合信号的无功分量到达放大器（102和106）。 由于没有反射的分量被反射回来，放大器（102和106）可以保持非线性，即使它们被用于放大包括幅度调制（AM）分量的幅度/相位调制信号。

公开(公告)号：WO1992012563A1

公开(公告)日：1992-07-23

申请号：PCT/US1991008786

申请日：1991-11-21

Applicant: MOTOROLA, INC.

Inventor： MOTOROLA, INC. ,  BURNS, Arthur, G. ,  STENGEL, Robert, E.

IPC: H02J07/04

CPC classification number: H02J7/34 ,  H02J7/0011 ,  H02J9/061 ,  Y10S320/24

Abstract: A rechargeable battery (10) comprises at least one cell (7) having a positive and a negative terminal. Switching regulation circuitry (9) coupled to the cell (7) is selectively used for regulating the battery output (28) and for regulating the charging (12) of the battery.

公开(公告)号：WO2007061523A2

公开(公告)日：2007-05-31

申请号：PCT/US2006/039626

申请日：2006-10-09

Applicant: MOTOROLA, INC. ,  THOMPSON, Bruce, M. ,  OOI, Leng, H. ,  STENGEL, Robert, E.

Inventor： THOMPSON, Bruce, M. ,  OOI, Leng, H. ,  STENGEL, Robert, E.

IPC: H04B1/04

CPC classification number: H04B1/0475

Abstract: A vector signal processor (80) can include a digital to time converter (DTC), an RF memory (RFM) or an electronically tunable transmission line (ETTL) (82), a mixer, or other phase shifter (70) for receiving an output of the DTC or the ETTL, and a controller for selectively controlling the harmonic processing of the DTC, RFM or the ETTL and the phase processing of the mixer. The vector signal processor can uncouple a relative phase of a fundamental signal with respect to harmonics of the fundamental signal. The vector signal processor uses selective phase processing of the fundamental signal and related harmonic components. In a specific embodiment, the vector signal processor cancels harmonics of the fundamental signal and more specifically can cancel a third harmonic of the fundamental signal.

Abstract translation: 矢量信号处理器（80）可以包括数字到时间转换器（DTC），RF存储器（RFM）或电子可调谐传输线（ETTL）（82），混频器或其他 用于接收DTC或ETTL的输出的移相器（70），以及用于选择性地控制DTC，RFM或ETTL的谐波处理和混频器的相位处理的控制器。 矢量信号处理器可以将基本信号的相对相位与基本信号的谐波解耦合。 矢量信号处理器使用基本信号和相关谐波分量的选择性相位处理。 在特定实施例中，矢量信号处理器消除基本信号的谐波，并且更具体地可以消除基本信号的三次谐波。

公开(公告)号：WO2006052416A2

公开(公告)日：2006-05-18

申请号：PCT/US2005/037858

申请日：2005-10-21

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  GRADISHAR, Thomas, L. ,  STENGEL, Robert, E.

IPC: H04L7/00

CPC classification number: H04L7/0083 ,  H03K5/133 ,  H03K5/135 ,  H03K2005/00286 ,  H03L7/0812 ,  H04L7/0337

Abstract: A DPC (300) includes: a frequency source (310) for generating a clock signal; a delay line (320) for receiving the clock signal and generating phase-shifted clock signals at output taps; a digital control device (330) for generating a control signal; and a windowing and selection circuit for generating the output signal, that includes sequential logic devices (500, 510, 520) and a combining network. A method for use in a DPC includes: receiving (400) a control signal based on a desired output signal that identifies a first output tap on the delay line; based on the control signal, selecting (410) at least two output taps on the delay line for receiving at least two different phase-shifted clock signals; and generating (420) an output signal based on the control signal and the received phase-shifted clock signals that is substantially the desired output signal.

Abstract translation: DPC（300）包括：频率源（310），用于生成时钟信号; 延迟线（320），用于接收时钟信号并在输出抽头产生相移时钟信号; 数字控制装置（330），用于产生控制信号; 以及用于产生输出信号的加窗和选择电路，其包括时序逻辑器件（500,510,520）和组合网络。 一种在DPC中使用的方法包括：基于标识延迟线上的第一输出抽头的期望输出信号来接收（400）控制信号; 基于所述控制信号，在所述延迟线上选择（410）至少两个输出抽头以接收至少两个不同的相移时钟信号; 以及基于所述控制信号和基本上为所述期望输出信号的接收到的相移时钟信号来生成（420）输出信号。

公开(公告)号：WO2004114091A3

公开(公告)日：2004-12-29

申请号：PCT/US2004/019788

申请日：2004-06-18

Applicant: MOTOROLA, INC. ,  CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

Inventor： CAFARO, Nicholas, G. ,  STENGEL, Robert, E.

IPC: H03L7/00

Abstract: A programmable skew clock signal generator has a frequency generator circuit (104) consistent with the invention produces an output signal F ϕ0 from a reference signal F ref A frequency accumulator (132, 152) is preloaded with a preload value P K1 and receives one reference signal cycle as a clock signal, receives a constant K 1 as an input thereto, with the frequency accumulator (132, 152) having a maximum count K MAX and producing an overflow output. A phase accumulator (136, 156) is preloaded with a preload value P C1 and receives one overflow cycle output from the frequency accumulator (132, 152) as a clock signal and receives a phase offset constant C 1 as an input thereto. The phase accumulator (136, 156) has a maximum count C MAX and produces a phase accumulator (136, 156) output. A delay line (320) is clocked by the reference signal F ref and produces a plurality of delayed reference clock signals at a plurality of tap outputs. A tap selecting circuit (140, 144; 160, 164) receives the phase accumulator output and selects at least one of the tap outputs in response thereto to produce an output F ϕ1 whose phase shift ϕ1 relative to F 0ϕ is a function of P K1 and P C1 .

公开(公告)号：WO2004107579A3

公开(公告)日：2004-12-09

申请号：PCT/US2004/015470

申请日：2004-05-18

Applicant: MOTOROLA, INC., a corporation of the State of Delaware ,  STENGEL, Robert, E.

Inventor： STENGEL, Robert, E.

IPC: H03L7/06

Abstract: A delay locked loop circuit (300) has a delay line (304) with coarse adjustment (322) and fine adjustment (360) inputs. The coarse adjustment input (322) provides an overall adjustment of all of the delay elements while the fine adjustment inputs (360) permit adjusting the individual delay value of each delay element. A first multiplexer (330) produces a first selected output while a second multiplexer (334) produces a second selected output. A measurement circuit (334) measures a difference between the first and second outputs. An error calculator (346) receives the output of the measurement circuit and calculates fine adjustment voltages for each of the selected delay elements. A tuning circuit (350) applies the fine adjustment voltages to the fine adjustment inputs.

公开(公告)号：WO2003052924A1

公开(公告)日：2003-06-26

申请号：PCT/US2002/039585

申请日：2002-12-10

Applicant: MOTOROLA, INC.

Inventor： OLSON, Scott, A. ,  STENGEL, Robert, E.

IPC: H03F1/00

CPC classification number: H03F1/3229

Abstract: A feedforward amplifier (150) according to the present invention uses a direct coupling of an amplifier stage (158) with the amplifier's load (R L ). The main amplifier (202) is coupled through a transmission line (210) to the load. This direct coupled amplifier stage (158) is driven by a signal that induces a very low impedance in parallel with the load to the error signal, but appears as an open circuit to the desired signal so that the desired signal from the main amplifier is substantially unaffected.

Abstract translation: 根据本发明的前馈放大器150使用放大器级158与放大器的负载RL的直接耦合。 主放大器202通过传输线210耦合到负载。 该直接耦合放大器级158由信号驱动，该信号与误差信号的负载并联地产生非常低的阻抗，但是作为对所需信号的开路呈现，使得来自主放大器的期望信号基本上不受影响。

公开(公告)号：WO2003012871A1

公开(公告)日：2003-02-13

申请号：PCT/US2002/015107

申请日：2002-05-14

Applicant: MOTOROLA, INC.

Inventor： HECK, Joseph, P. ,  BOCKELMAN, David, E. ,  STENGEL, Robert, E.

IPC: H01L27/06

CPC classification number: H01L21/8221 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02505 ,  H01L21/02513 ,  H01L21/02521 ,  H01L21/8258 ,  H01L27/0605 ,  H01L27/0688 ,  H01L27/15 ,  H01L2924/00011 ,  H01S5/021 ,  H01S5/0261 ,  H01S2301/173 ,  H03F1/18 ,  H01L2224/80001

Abstract: High quality epitaxial layers of monocrystalline materials (66) can be grown overlying monocrystalline substrates (52) such as large silicon wafers by forming a compliant substrate for growing the monocrystalline layers. Devices(56) may be formed in the silicon wafer prior to growing the high quality epitaxial layers. Then, to achieve the formation of a compliant substrate, an accommodating buffer layer (65) is grown on silicon wafer. The accommodating buffer layer is a layer of monocrystalline oxide spaced apart from the silicon wafer by an amorphous interface layer (62) of silicon oxide. The amorphous interface layer dissipates strain and permits the growth of a high quality monocrystalline oxide accommodating buffer layer. The accommodating buffer layer is lattice matched to both the underlying silicon wafer and the overlying monocrystalline material layer. Compound devices (68) are then formed on the overlying monocrystalline layer. Any lattice mismatch between the accommodating buffer layer and the underlying silicon substrate is taken care of by the amorphous interface layer. In addition, formation of a compliant substrate may include utilizing surfactant enhanced epitaxy, epitaxial growth of single crystal silicon onto single crystal oxide, and epitaxial growth of Zintl phase materials. Silicon devices and circuits (e.g., CMOS circuits) in the silicon wafer are wired (70) to the compound devices (e.g., MESFETs, HBTs, HEMTs, PHEMTs, etc.), forming an electrical connection therebetween.

Abstract translation: 通过形成用于生长单晶层的顺应性衬底，可以将单晶材料（66）的高质量外延层生长在覆盖单晶衬底（52），例如大硅晶片上。 在生长高质量外延层之前，可以在硅晶片中形成器件（56）。 然后，为了形成顺应性衬底，在硅晶片上生长容纳缓冲层（65）。 容纳缓冲层是通过氧化硅的非晶界面层（62）与硅晶片间隔开的单晶氧化物层。 非晶界面层消耗应变并允许高质量单晶氧化物容纳缓冲层的生长。 容纳缓冲层与下面的硅晶片和上覆的单晶材料层晶格匹配。 然后在覆盖的单晶层上形成复合器件（68）。 通过非晶界面层处理容纳缓冲层和底层硅衬底之间的任何晶格失配。 此外，顺应性衬底的形成可以包括利用表面活性剂增强的外延，将单晶硅外延生长到单晶氧化物上，以及Zintl相材料的外延生长。 硅晶片中的硅器件和电路（例如，CMOS电路）被连线（70）到复合器件（例如，MESFET，HBT，HEMT，PHEMT等），在它们之间形成电连接。

公开(公告)号：WO1997038505A1

公开(公告)日：1997-10-16

申请号：PCT/US1997005484

申请日：1997-04-02

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  O'DEA, Robert, J. ,  STENGEL, Robert, E.

IPC: H04L01/00

CPC classification number: H04L27/2032 ,  H04L27/368

Abstract: A modulated signal, having a varying magnitude signal envelope, is conditioned, such as to facilitate amplification (500). Minimum values are determined values for portions of the signal envelope (520, 530), and a window expansion function applied to scale each portion of the signal envelope having a minimum value below a particular threshold, such that each scaled portion has a new minimum value of at least the particular threshold (535, 540, 550, 555).

Abstract translation: 具有变化的幅度信号包络的调制信号被调节，以便于放大（500）。 最小值是对于信号包络（520,530）的部分的确定值，以及窗口扩展功能，用于缩放具有低于特定阈值的最小值的信号包络的每个部分，使得每个缩放部分具有新的最小值 至少具有特定阈值（535,540,550,555）。

公开(公告)号：WO1995005028A1

公开(公告)日：1995-02-16

申请号：PCT/US1994009036

申请日：1994-08-05

Applicant: MOTOROLA INC.

Inventor： MOTOROLA INC. ,  MURI, David, L. ,  STENGEL, Robert, E.

IPC: H03F03/217

CPC classification number: H03F3/2173

Abstract: Pulsewidth-modulated amplifier (100) includes a controller (102) which provides for a set of compensated signals (114, 158 and 160). The compensated signals are used for driving a speaker (136). Controller (100) includes a storage area for storing distortion characteristics for the amplifier for a predetermined operational frequency range. The compensated drive signals (114, 158 and 160) help compensate for the electrical non-linear distortions that occur in amplifier (100) and thereby help reduce the output distortion of amplifier (100).

Abstract translation: 脉宽调制放大器（100）包括提供一组补偿信号（114,158和160）的控制器（102）。 补偿信号用于驱动扬声器（136）。 控制器（100）包括用于在预定工作频率范围内存储用于放大器的失真特性的存储区域。 经补偿的驱动信号（114,158和160）有助于补偿放大器（100）中发生的电非线性失真，从而有助于减小放大器（100）的输出失真。