公开(公告)号：US08767467B2

公开(公告)日：2014-07-01

申请号：US13970055

申请日：2013-08-19

Applicant: Micron Technology, Inc.

Inventor： Krishna K. Parat ,  Akira Goda ,  Koichi Kawal ,  Brian J. Soderling ,  Jeremy Binfet ,  Arnaud A. Furnemont ,  Tejas Krishnamohan ,  Tyson M. Stichka ,  Giuseppina Puzzilli

IPC: G11C16/04

CPC classification number: G11C29/765 ,  G11C11/5628 ,  G11C16/0483 ,  G11C16/16 ,  G11C16/349 ,  G11C29/789

Abstract: Memory devices and methods are disclosed, including a method involving erasing a block of memory cells. After erasing the block, and before subsequent programming of the block, a number of bad strings in the block are determined based on charge accumulation on select gate transistors. The block is retired from use if the number of bad strings exceeds a threshold. Additional embodiments are disclosed.

Abstract translation: 公开了存储器件和方法，包括涉及擦除存储器单元块的方法。 在擦除块之后，并且在块的后续编程之前，基于选择栅晶体管上的电荷积累来确定块中的多个不良串。 如果坏字符串的数量超过阈值，则该块将从使用中退出。 公开了另外的实施例。

公开(公告)号：US11797216B2

公开(公告)日：2023-10-24

申请号：US17867489

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C29/50

CPC classification number: G06F3/0652 ,  G06F3/0604 ,  G06F3/0619 ,  G06F3/0649 ,  G06F3/0653 ,  G06F3/0679 ,  G11C11/5642 ,  G11C16/349 ,  G11C29/50004

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

公开(公告)号：US20220350520A1

公开(公告)日：2022-11-03

申请号：US17867489

申请日：2022-07-18

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, JR. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo' Righetti

IPC: G06F3/06 ,  G11C11/56 ,  G11C16/34 ,  G11C29/50

Abstract: A signal associated with performance of a memory operation can be applied to a memory cell of a first group of memory cells that have undergone PECs within a first range. The signal can have a first magnitude corresponding to a second range of PECs. Whether differences between a first target voltage and the signal and between a second target voltage and the applied signal are at least the threshold value can be determined. Responsive to determining that the differences are at least the threshold value, the first group of memory cells can be associated with a first calibration cluster and the signal having a second magnitude corresponding to a third range of PECs can be applied to a memory cell of a second group of memory cells that have undergone respective quantities of PECs within the second range.

公开(公告)号：US20220342813A1

公开(公告)日：2022-10-27

申请号：US17302064

申请日：2021-04-22

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Giuseppina Puzzilli ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe ,  James Fitzpatrick ,  Shyam Sunder Raghunathan ,  Violante Moschiano ,  Tecla Ghilardi

IPC: G06F12/02 ,  G11C29/52 ,  G11C16/34

Abstract: A highly read data manager of a memory device receives a request to perform receives a request to perform a data relocation operation on a first wordline of a plurality of wordlines for a memory device, the memory device comprising a plurality of multi-level memory cells, wherein each multi-level memory cell comprises a plurality of pages; determines at the first wordline comprises data stored at one or more high read disturb pages of the plurality of pages; determines whether the data comprises a characteristic that satisfies a threshold criterion in relation to additional data stored on additional wordlines of the plurality of wordlines; responsive to determining that the data comprises the characteristic that satisfies the threshold criterion, identifies one or more low read disturb pages of the plurality of pages of a target wordline for relocating the data; and responsive to identifying the one or more low read disturb pages of the target wordline, stores at least a portion of the data at the one or more low read disturb pages of the target wordline.

公开(公告)号：US20220308778A1

公开(公告)日：2022-09-29

申请号：US17212437

申请日：2021-03-25

Applicant: Micron Technology, Inc.

Inventor： Pitamber Shukla ,  Scott Anthony Stoller ,  Niccolo' Righetti ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A trigger condition associated with latent read disturb in a memory device is detected. In response to detecting the trigger condition associated with latent read disturb, one or more blocks in the memory device that are impacted by the trigger condition are placed in a stable state to mitigate latent read disturb in the one or more blocks.

公开(公告)号：US11430528B2

公开(公告)日：2022-08-30

申请号：US17001757

申请日：2020-08-25

Applicant: Micron Technology, Inc.

Inventor： Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Karl D. Schuh ,  Jeffrey S. McNeil, Jr. ,  Kishore K. Muchherla ,  Ashutosh Malshe ,  Niccolo′ Righetti

IPC: G11C16/34 ,  G11C16/04

Abstract: A change in a read window of a group of memory cells of a memory device that has undergone a plurality of program/erase cycles (PECs) can be determined. read voltage can be determined based at least in part on the determined change in the read window.

公开(公告)号：US11385819B2

公开(公告)日：2022-07-12

申请号：US16995682

申请日：2020-08-17

Applicant: Micron Technology, Inc.

Inventor： Kishore K. Muchherla ,  Niccolo' Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F3/06

Abstract: A system includes a processing device and trigger circuitry to signal the processing device responsive, at least in part, based on a determination that a trigger event has occurred. The system can further include a memory device communicatively coupled to the processing device. The memory device can include a cyclic buffer partition portion having a first endurance characteristic and a first reliability characteristic associated therewith. The memory device can further include a snapshot partition portion coupled to the cyclic buffer partition portion via hold-up capacitors. The snapshot partition portion can have a second endurance characteristic and a second reliability characteristic associated therewith. The processing device can perform operations including writing received data sequentially to the cyclic buffer partition portion and writing, based at least in part on the determination that the trigger event has occurred, data from the cyclic buffer partition portion to the snapshot partition portion.

公开(公告)号：US20220197771A1

公开(公告)日：2022-06-23

申请号：US17691957

申请日：2022-03-10

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, JR. ,  Niccolo' Righetti ,  Kishore K. Muchherla ,  Akira Goda ,  Todd A. Marquart ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/30 ,  G06F11/07 ,  G06F1/30 ,  G11C5/14 ,  G11C16/34

Abstract: A method includes writing received data sequentially to a particular location of a cyclic buffer of a memory device according to a first set of threshold voltage distributions. The method further includes performing a touch up operation on the particular location by adjusting the first set of threshold voltage distributions of the data to a second set of threshold voltage distributions in response to a determination that a trigger event has occurred. The second set of threshold voltage distributions can have a larger read window between adjacent threshold voltage distributions of the second set than that of the first set of threshold voltage distributions.

公开(公告)号：US20220189571A1

公开(公告)日：2022-06-16

申请号：US17122758

申请日：2020-12-15

Applicant: Micron Technology, Inc.

Inventor： Jeffrey S. McNeil, JR. ,  Karl D. Schuh ,  Vamsi Pavan Rayaprolu ,  Giuseppina Puzzilli ,  Kishore K. Muchherla ,  Gil Golov ,  Todd A. Marquart ,  Jiangang Wu ,  Niccolo' Righetti ,  Ashutosh Malshe

IPC: G11C16/34 ,  G11C16/16 ,  G11C16/26 ,  G11C16/32 ,  G11C16/30

Abstract: Instructions can be executed to adjust a trim at first intervals until a quantity of program/erase cycles (PEC) have occurred. The trim defines a valley width between data states. Instructions can be executed to adjust the trim at second intervals, greater than the first intervals, after the quantity of PEC have occurred.

公开(公告)号：US11301346B2

公开(公告)日：2022-04-12

申请号：US17005114

申请日：2020-08-27

Applicant: Micron Technology, Inc.

Inventor： Todd A. Marquart ,  Niccolo′ Righetti ,  Jeffrey S. McNeil, Jr. ,  Akira Goda ,  Kishore K. Muchherla ,  Mark A. Helm ,  Gil Golov ,  Jeremy Binfet ,  Carmine Miccoli ,  Giuseppina Puzzilli

IPC: G06F11/00 ,  G06F11/30 ,  G06F11/14 ,  G06F11/32 ,  G06F1/30 ,  G06F11/07

Abstract: A system includes a processing device and a memory device coupled to the processing device. The memory device can include a cyclic buffer portion and a snapshot portion. The processing device can store time based telemetric sensor data in the cyclic buffer portion, copy an amount of the telemetric sensor data from the cyclic buffer portion to the snapshot portion in response to a trigger event, operate the cyclic buffer portion with a first trim tailored to a performance target of the cyclic buffer portion, and operate the snapshot portion with a second trim tailored to a performance target of the snapshot portion.