公开(公告)号：US20220269559A1

公开(公告)日：2022-08-25

申请号：US17741940

申请日：2022-05-11

Applicant: Micron Technology, Inc.

Inventor： Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Xiangang Luo ,  Vamsi Pavan Rayaprolu ,  Ashutosh Malshe

IPC: G06F11/10 ,  G06F11/14

Abstract: A variety of applications can include use of parity groups in a memory system with the parity groups arranged for data protection of the memory system. Each parity group can be structured with multiple data pages in which to write data and a parity page in which to write parity data generated from the data written in the multiple data pages. Each data page of a parity group can have storage capacity to include metadata of data written to the data page. Information can be added to the metadata of a data page with the information identifying an asynchronous power loss status of data pages that precede the data page in an order of writing data to the data pages of the parity group. The information can be used in re-construction of data in the parity group following an uncorrectable error correction code error in writing to the parity group.

公开(公告)号：US20220246214A1

公开(公告)日：2022-08-04

申请号：US17724940

申请日：2022-04-20

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C16/10 ,  G06F3/06 ,  G11C11/56 ,  G11C16/26

Abstract: A memory system to store multiple bits of data in a memory cell. A memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of bit values according to a mapping between bit value combinations and threshold levels. The threshold levels are partitioned into groups, each containing a subset of the threshold levels and having associated read voltages separating threshold levels in the subset. A group identification of a first group, among the groups, containing the first level is determined for the memory cell. The memory device applies read voltages of different groups, interleaved in an increasing order in a sequence, to read the memory cell when a read voltage applied is associated with the first group. The data bits read back from the memory cell are used to finely program the threshold voltage of the memory cell.

公开(公告)号：US20220199154A1

公开(公告)日：2022-06-23

申请号：US17127459

申请日：2020-12-18

Applicant: Micron Technology, Inc.

Inventor： Phong Sy Nguyen ,  James Fitzpatrick ,  Kishore Kumar Muchherla

IPC: G11C11/56 ,  G11C16/10 ,  G11C16/26

Abstract: A memory system to store multiple bits of data in a memory cell. After receiving the data bits, a memory device coarsely programs a threshold voltage of the memory cell to a first level representative of a combination of values of the data bits according to a mapping between combinations of values of bits and threshold levels. The threshold levels are partitioned into a plurality of groups, each containing a subset of the threshold levels. XOR (or XNOR) is used to combine the data bits into bits of a group identification of a first group, among the plurality of groups, that contains the first level. The memory device reads, using the group identification, the data bits back from the first memory cell to finely program the threshold voltage of the memory cell to represent the data bits.

公开(公告)号：US20220189517A1

公开(公告)日：2022-06-16

申请号：US17463789

申请日：2021-09-01

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Eric N. Lee ,  Kishore Kumar Muchherla ,  Jeffrey S. McNeil ,  Jung-Sheng Hoei

IPC: G11C7/10 ,  G11C7/14 ,  G11C7/22

Abstract: Memory devices might include an array of memory cells, a plurality of access lines, and control logic. The array of memory cells includes a plurality of strings of series-connected memory cells. Each access line of the plurality of access lines is connected to a control gate of a respective memory cell of each string of series-connected memory cells of the plurality of strings of series-connected memory cells. The control logic is configured to: open the array of memory cells for multiple read operations; read first page data from respective memory cells coupled to a selected access line of the plurality of access lines; read second page data from the respective memory cells coupled to the selected access line; and close the array of memory cells subsequent to reading the first page data and the second page data.

公开(公告)号：US20220171713A1

公开(公告)日：2022-06-02

申请号：US17399997

申请日：2021-08-11

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Ashutosh Malshe ,  Sampath Ratnam ,  Kishore Kumar Muchherla ,  Peter Feeley

IPC: G06F12/10 ,  G06F12/02

Abstract: At least one source physical memory block stored in a memory device is identified. The source physical memory block comprises at least one logical unit. A determination is made as to whether an age characteristic of the logical unit satisfies a threshold criterion. A storage classification is determined for the logical unit based on whether the age characteristic of the logical unit satisfies the threshold criterion. The classification comprises a hot data classification or a cold data classification. A target physical memory block is identified based on the storage classification determined for the logical unit, and the logical unit is stored in the identified target physical memory block.

公开(公告)号：US20220164106A1

公开(公告)日：2022-05-26

申请号：US17100712

申请日：2020-11-20

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Shane Nowell ,  Michael Sheperek ,  Vamsi Pavan Rayaprolu ,  Kishore Kumar Muchherla

IPC: G06F3/06

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to determine that a first block family of a plurality of block families of the memory device and a second block family of the plurality of block families satisfy a proximity condition; determine whether the first block family and the second block family meet a time-based combining criterion corresponding to the proximity condition; and responsive to determining that the first block family and the second block family meet the time-based combining criterion, merge the first block family and the second block family.

公开(公告)号：US11335394B2

公开(公告)日：2022-05-17

申请号：US17238846

申请日：2021-04-23

Applicant: Micron Technology, Inc.

Inventor： Gianni Stephen Alsasua ,  Harish Reddy Singidi ,  Kishore Kumar Muchherla ,  Sampath Ratnam ,  Ashutosh Malshe ,  Vamsi Pavan Rayaprolu ,  Renato Padilla, Jr.

IPC: G11C7/00 ,  G11C11/406 ,  G06F13/16 ,  G11C7/04

Abstract: Devices and techniques for temperature informed memory refresh are described herein. A temperature counter can be updated in response to a memory device write performed under an extreme temperature. Here, the write is performed on a memory device element in the memory device. The memory device element can be sorted above other memory device elements in the memory device based on the temperature counter. Once sorted to the top of these memory device elements, a refresh can be performed the memory device element.

公开(公告)号：US20220129168A1

公开(公告)日：2022-04-28

申请号：US17573224

申请日：2022-01-11

Applicant: Micron Technology, Inc.

Inventor： Kulachet Tanpairoj ,  Sebastien Andre Jean ,  Kishore Kumar Muchherla ,  Ashutosh Malshe ,  Jianmin Huang

IPC: G06F3/06 ,  G06F12/0811 ,  G06F12/02

Abstract: Disclosed in some examples are memory devices which feature customizable Single Level Cell (SLC) and Multiple Level Cell (MLC) configurations. The SLC memory cells serve as a high-speed cache providing SLC level performance with the storage capacity of a memory device with MLC memory cells. The proportion of cells configured as MLC vs the proportion that are configured as SLC storage may be configurable, and in some examples, the proportion may change during usage based upon configurable rules based upon memory device metrics. In some examples, when the device activity is below an activity threshold, the memory device may skip the SLC cache and place the data directly into the MLC storage to reduce power consumption.

公开(公告)号：US20220108752A1

公开(公告)日：2022-04-07

申请号：US17542694

申请日：2021-12-06

Applicant: Micron Technology, Inc.

Inventor： Michael Sheperek ,  Kishore Kumar Muchherla ,  Mustafa N. Kaynak ,  Vamsi Pavan Rayaprolu ,  Bruce A. Liikanen ,  Larry J. Koudele

IPC: G11C16/20 ,  G11C16/34 ,  G11C16/32 ,  G11C16/30 ,  G11C16/26

Abstract: An example memory sub-system includes a memory device and a processing device, operatively coupled to the memory device. The processing device is configured to program a first block in a first die of the memory device and a second block in a second die of the memory device, wherein the first die and the second die are assigned to a die group; and associate the die group with a threshold voltage offset bin.

公开(公告)号：US20220083243A1

公开(公告)日：2022-03-17

申请号：US16948305

申请日：2020-09-11

Applicant: Micron Technology, Inc.

Inventor： Kishore Kumar Muchherla ,  Karl D. Schuh ,  Jiangang Wu ,  Mustafa N. Kaynak ,  Devin M. Batutis ,  Xiangang Luo

IPC: G06F3/06

Abstract: A system includes a memory device having multiple of dice and a processing device operatively coupled to the memory device. The processing device performs operations including receiving memory operations to program sets of pages of data across at least a subset of the plurality of dice and identifying a plurality of the sets of pages experiencing a variation in a data state metric satisfying a threshold criterion. The operations further include partitioning, into a set of partitions, a set of pages of the plurality of the sets of pages, programming the set of partitions to the plurality of dice, and storing, in a metadata table, at least one bit to indicate that the first set of pages is partitioned.