公开(公告)号：US11011468B2

公开(公告)日：2021-05-18

申请号：US16676291

申请日：2019-11-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/528 ,  H01L23/48 ,  H01L23/482 ,  H01L21/768 ,  H01L21/683 ,  H01L21/304 ,  H01L21/283 ,  H01L23/538

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure includes a semiconductor substrate, a target layer, a plurality of metal pads, a plurality of conductive lines, a plurality of conductive plugs, an isolating liner, and a plurality of metal contacts. The semiconductor substrate has a front surface, a rear surface opposite to the front surface, and an implanted region connected to the rear surface. The target layer is disposed over the front surface. The metal pads are disposed over the target layer. The plurality of conductive lines are disposed within the semiconductor substrate and the target layer and connected to the metal pads. The conductive plugs are disposed in the implanted region. The isolating liner encircles the conductive plugs. The metal contacts are disposed over the conductive lines and the conductive plugs.

公开(公告)号：US10985134B2

公开(公告)日：2021-04-20

申请号：US16186100

申请日：2018-11-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/76 ,  H01L21/78 ,  H01L23/00 ,  H01L21/768

Abstract: The present disclosure provides a method of manufacturing stacked wafers. The method includes receiving a first wafer having semiconductor components formed therein; receiving a second wafer having semiconductor components formed therein; attaching the first wafer to the second wafer; and forming a set of stacked wafers by thinning the second wafer, using the first wafer as a holder.

公开(公告)号：US10734338B2

公开(公告)日：2020-08-04

申请号：US16268954

申请日：2019-02-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Chiang-Lin Shih ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/522

Abstract: The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a method of manufacturing the semiconductor structure. The bonding pad includes an inner ring member, an outer ring member, and multiple bridge members. The inner ring member has a pair of first inner edges opposite to each other, a pair of second inner edges opposite to each other, and multiple third inner edges for connecting the first inner edges to the second inner edges. The outer ring member surrounds the inner ring member and has a pair of first outer edges opposite to each other, a pair of second outer edges opposite to each other, and multiple third outer edges for connecting the first outer edges to the second outer edges. The bridge members are disposed between the inner ring member and the outer ring member for connecting the inner ring member to the outer ring member.

公开(公告)号：US10734308B2

公开(公告)日：2020-08-04

申请号：US16212072

申请日：2018-12-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/48 ,  H01L21/768 ,  H01L23/532 ,  H01L21/304 ,  H01L25/065

Abstract: The present disclosure relates to a semiconductor device and a method of manufacturing the same. The semiconductor device includes a semiconductor substrate and at least one through silicon via. The through silicon via includes a conductive plug, a first insulation layer, and a diffusion barrier layer. The conductive plug penetrates through the semiconductor substrate. The first insulation layer surrounds the conductive plug. The diffusion barrier layer is disposed between the conductive plug and the first insulation layer, and is utilized to prevent out-diffusion of dopant impurities from the conductive plug to the semiconductor substrate.

公开(公告)号：US12272413B2

公开(公告)日：2025-04-08

申请号：US17838726

申请日：2022-06-13

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: G11C17/16 ,  H01L23/525 ,  H10B20/25

Abstract: A method of fabricating a semiconductor device includes steps of forming a first insulative film on a substrate; forming a first electrode on the first insulative film; implanting dopants in the substrate to form a plurality of first impurity regions on either side of the first electrode; depositing a capping layer to cover the first electrode; forming a second insulative film on portions of the substrate exposed through the first electrode and the capping layer; forming a second electrode disposed over the capping layer and portions of the second insulative film; removing portions of the second insulative film on either side of the second electrode; and implanting dopants in portions of the substrate exposed by the second insulative film to form a plurality of second impurity regions. With the configurations of semiconductor device, the current for blowing the semiconductor device can increase while applying the same programming voltage.

公开(公告)号：US12191253B2

公开(公告)日：2025-01-07

申请号：US17839796

申请日：2022-06-14

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L23/525

Abstract: A semiconductor device is provided. The semiconductor device includes a substrate, a fuse element, and a fuse medium. The fuse element is disposed within the substrate. The fuse medium surrounds a lateral surface of the fuse element.

公开(公告)号：US12167591B2

公开(公告)日：2024-12-10

申请号：US17678212

申请日：2022-02-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Wei-Zhong Li ,  Hsih-Yang Chiu

IPC: H10B20/20

Abstract: The present application discloses a semiconductor device, including a substrate; an isolation layer positioned in the substrate and defining an active area of the substrate, wherein the active area includes a transistor portion and a programmable portion extending from the transistor portion; a gate structure positioned on the transistor portion; a drain region positioned in the programmable portion and the transistor portion, and adjacent to the gate structure; a source region positioned in the transistor portion, adjacent to the gate structure, and opposite to the drain region with the gate structure interposed therebetween; a middle insulating layer positioned on the programmable portion; and an upper conductive layer positioned on the middle insulating layer. The drain region in the programmable portion, the middle insulating layer, and the upper conductive layer together configure a programmable structure.

公开(公告)号：US12148731B2

公开(公告)日：2024-11-19

申请号：US17715272

申请日：2022-04-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/76 ,  H01L23/00

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes providing an interconnection structure. The method also includes forming a first dielectric layer on the interconnection structure. The method further includes forming a sacrificial pattern on the first dielectric layer. The method also includes forming an RDL on the first dielectric layer and the sacrificial pattern. The method further includes removing the sacrificial pattern to form an air cavity within the RDL.

公开(公告)号：US12068203B2

公开(公告)日：2024-08-20

申请号：US17511231

申请日：2021-10-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Hsih-Yang Chiu

IPC: H01L21/8234 ,  H01L21/761 ,  H01L23/00

CPC classification number: H01L21/823481 ,  H01L21/761 ,  H01L21/823475 ,  H01L24/80 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: A method for manufacturing a semiconductor device structure including a doped region under an isolation feature. The method includes providing a substrate having a first surface and a second surface opposite to the first surface, wherein the substrate comprises a first well region with a first conductive type; forming an isolation feature extending from the second surface of the substrate; forming a first transistor and a second transistor adjacent to the second surface of the substrate; forming a first doped region under the isolation feature, wherein the first doped region has a second conductive type different from the first conductive type; and providing a circuit structure on the first surface of the substrate, wherein the circuit structure is configured to transmit or provide a voltage electrically coupled with the first doped region.

公开(公告)号：US11984389B2

公开(公告)日：2024-05-14

申请号：US18305374

申请日：2023-04-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chien-Chung Wang ,  Hsih-Yang Chiu

IPC: H01L23/00 ,  H01L21/48 ,  H01L23/498

CPC classification number: H01L23/49811 ,  H01L21/4853 ,  H01L24/48 ,  H01L2224/48225 ,  H01L2924/1533

Abstract: An integrated circuit package structure includes a circuit board, an integrated circuit die and a conductive stair structure. The circuit has an upper surface. The integrated circuit die is located on the upper surface of the circuit board. The conductive stair structure is located on the upper surface of the circuit board. The conductive stair structure includes steps along a first direction substantially perpendicular to the upper surface of the circuit board. The steps have different heights relative to the upper surface of the circuit board.