公开(公告)号：US12295137B2

公开(公告)日：2025-05-06

申请号：US18213977

申请日：2023-06-26

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo ,  Chiang-Lin Shih ,  Hsih-Yang Chiu

IPC: H10B12/00 ,  H01L23/528 ,  H01L23/532

Abstract: A semiconductor device and method for manufacturing the same are provided. The semiconductor device includes a substrate, a bonding structure, a bit line, and a word line. The bonding structure is disposed on the substrate. The bit line is disposed on the bonding structure. The channel layer is disposed on the bit line. The word line surrounds the channel layer. The bonding structure includes a dielectric material.

公开(公告)号：US11315928B2

公开(公告)日：2022-04-26

申请号：US17014282

申请日：2020-09-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Tseng-Fu Lu ,  Jeng-Ping Lin

IPC: H01L27/108 ,  H01L23/535 ,  H01L21/74

Abstract: The present disclosure provides a semiconductor structure. The semiconductor structure comprises a substrate having a first top surface. An active region is surrounded by an isolation region in the substrate. A buried power line and a buried signal line are disposed within the substrate and in the active region. A first circuit layer is disposed on the first top surface of the substrate to cover the buried power line and the buried signal line. A second circuit layer is disposed on the first top surface of the substrate and separated from the first circuit layer. A cell capacitor is disposed on and electrically coupled to the first circuit layer.

公开(公告)号：US10262862B1

公开(公告)日：2019-04-16

申请号：US15894095

申请日：2018-02-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Shing-Yih Shih

IPC: H01L21/311 ,  H01L21/033 ,  H01L21/28 ,  H01L21/768 ,  H01L21/762

Abstract: The present disclosure provides a method of forming fine interconnection for semiconductor devices. The method includes the following steps: A substrate is provided. A first core layer is formed over the substrate. The first core layer includes a base portion, a plurality of extending line portions extending from the base portion along a first direction, and a plurality of isolated line portions isolated from the base portion. Subsequently, a spacer is formed on the sidewalls of the first core layer. A second core layer is then formed to over the substrate. The second core layer includes a plurality of surrounding line portions surrounding the plurality of isolated line portions, and includes a plurality of enclosed line portions enclosed by the plurality of extending line portions. The spacer is removed to form a plurality of openings between the first core layer and the second core layer. The first core layer and the second core layer are alternately arranged along a second direction perpendicular to the first direction after removing the spacer.

公开(公告)号：US11776924B2

公开(公告)日：2023-10-03

申请号：US17546275

申请日：2021-12-09

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Pei-Jhen Wu ,  Ching-Hung Chang ,  Hsih-Yang Chiu

IPC: H01L23/522 ,  H01L23/00 ,  H01L21/768

CPC classification number: H01L24/05 ,  H01L21/76895 ,  H01L23/5226 ,  H01L24/03 ,  H01L24/08 ,  H01L24/80 ,  H01L2224/039 ,  H01L2224/05547 ,  H01L2224/05556 ,  H01L2224/05571 ,  H01L2224/05647 ,  H01L2224/08147 ,  H01L2224/80895 ,  H01L2224/80896

Abstract: The present disclosure provides a method of manufacturing a semiconductor device. The method includes forming an interconnect layer on a semiconductor component, wherein the interconnect layer contains at least one metal pad electrically coupled to the semiconductor component; depositing an insulating layer on the interconnect layer; depositing a bonding dielectric on the insulating layer; and forming a re-routing layer penetrating through the bonding dielectric and the insulating layer and contacting the interconnect layer.

公开(公告)号：US11574911B2

公开(公告)日：2023-02-07

申请号：US17544663

申请日：2021-12-07

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Chih-Hung Chen ,  Szu-Yao Chang

IPC: H01L27/108

Abstract: The present application discloses a method for fabricating a semiconductor device with a protruding contact. The method includes providing a substrate; forming a bit line structure on the substrate; forming a capacitor contact structure next to the bit line structure; recessing a top surface of the bit line structure; and forming a landing pad layer covering a portion of a top surface of the capacitor contact structure and an upper portion of a sidewall of the capacitor contact structure.

公开(公告)号：US20220293561A1

公开(公告)日：2022-09-15

申请号：US17199458

申请日：2021-03-12

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo ,  Hsih Yang Chiu ,  Ching Hung Chang ,  Chiang-Lin Shih

IPC: H01L25/065 ,  H01L25/00 ,  H01L23/00

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a fusion-bonding interface is formed between the first device wafer and the second device wafer, wherein the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

公开(公告)号：US10734338B2

公开(公告)日：2020-08-04

申请号：US16268954

申请日：2019-02-06

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Pei-Jhen Wu ,  Chiang-Lin Shih ,  Hsih-Yang Chiu

IPC: H01L23/52 ,  H01L23/00 ,  H01L23/522

Abstract: The present disclosure relates to a multi-ring bonding pad, a semiconductor structure having the multi-ring bonding pad, and a method of manufacturing the semiconductor structure. The bonding pad includes an inner ring member, an outer ring member, and multiple bridge members. The inner ring member has a pair of first inner edges opposite to each other, a pair of second inner edges opposite to each other, and multiple third inner edges for connecting the first inner edges to the second inner edges. The outer ring member surrounds the inner ring member and has a pair of first outer edges opposite to each other, a pair of second outer edges opposite to each other, and multiple third outer edges for connecting the first outer edges to the second outer edges. The bridge members are disposed between the inner ring member and the outer ring member for connecting the inner ring member to the outer ring member.

公开(公告)号：US20240055390A1

公开(公告)日：2024-02-15

申请号：US18491813

申请日：2023-10-23

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo ,  Hsih Yang Chiu ,  Ching Hung Chang ,  Chiang-Lin Shih

IPC: H01L23/00 ,  H01L25/00 ,  H01L25/065

CPC classification number: H01L24/80 ,  H01L25/50 ,  H01L25/0657 ,  H01L24/08 ,  H01L2924/1436 ,  H01L2224/80894 ,  H01L2224/08146 ,  H01L2225/06541 ,  H01L2224/8038

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

公开(公告)号：US11842979B2

公开(公告)日：2023-12-12

申请号：US17198252

申请日：2021-03-11

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Yi-Jen Lo ,  Hsih Yang Chiu ,  Ching Hung Chang ,  Chiang-Lin Shih

IPC: H01L25/065 ,  H01L23/00 ,  H01L25/00

CPC classification number: H01L24/80 ,  H01L24/08 ,  H01L25/0657 ,  H01L25/50 ,  H01L2224/08146 ,  H01L2224/8038 ,  H01L2224/80894 ,  H01L2225/06541 ,  H01L2924/1436

Abstract: The disclosure provides a method of manufacturing a semiconductor device including bonding a second device wafer to a first device wafer, such that a first bonding interface including a dielectric-to-dielectric bonding interface and a metal-to-metal bonding interface is formed between the first device wafer and the second device wafer, wherein the second device wafer is electrically coupled to the first device wafer, and a function of the first device wafer and the second device wafer are the same kind of device wafer. A semiconductor device is also provided.

公开(公告)号：US11658070B2

公开(公告)日：2023-05-23

申请号：US17643182

申请日：2021-12-08

Applicant: NANYA TECHNOLOGY CORPORATION

Inventor： Chiang-Lin Shih ,  Shing-Yih Shih

IPC: H01L21/768 ,  H01L23/00 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L21/76831 ,  H01L23/481 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/32057 ,  H01L2224/32145 ,  H01L2224/83896 ,  H01L2224/83931

Abstract: A method of forming a semiconductor structure includes following steps. A first wafer is bonded to a second wafer, in which the first wafer includes a first substrate and a first conductive pad above a first surface of the first substrate, and the second wafer comprises a second substrate and a second conductive pad above a second surface of the second substrate. A mask layer is formed above the first substrate. The mask layer and the first substrate are etched to form a first opening in the first substrate. A sacrificial spacer is formed in the first substrate at a sidewall of the first opening. The first conductive pad is etched to form a second opening communicated to the first opening. A conductive material is filled in the first opening and the second opening to form a conductive structure interconnecting the first and second conductive pads.