公开(公告)号：FI750169A

公开(公告)日：1975-07-31

申请号：FI750169

申请日：1975-01-23

Applicant: RCA CORP

Inventor： STECKLER STEVEN ALAN ,  LIMBERG ALLEN LEROY

IPC: H04N5/06 ,  H04N5/04 ,  H04N5/08 ,  H04N5/12 ,  H04N5/213

Abstract: A dual mode deflection synchronizing system includes a resettable counter which generates noise-free internal synchronizing signals and signals representative of the interval during which external vertical synchronizing signals should be received provided the counter is properly synchronized. A sync signal verification detector is coupled to the source of external vertical sync signals and to a mode switch so that if the external signals arrive during this prediction interval as determined by the sync signal verification detector the system continues to operate in a synchronized mode on its internally generated synchronizing signals. If the external signals do not arrive during this prediction interval, the mode switch switches the system into a non-synchronized mode. A vertical sync signal detector which is also coupled to the source of external sync signals and to the mode switch begins to search for an external signal which has the time duration characteristic of an authentic external synchronizing signal. Until such a signal is received, the system continues to be synchronized by internal synchronizing signals generated by the resettable counter. When such a signal is received, the vertical sync signal detector resets the counter to correct its synchronization with the received external vertical synchronizing signal and toggles the mode switch to return the system to its synchronized mode of operation.

公开(公告)号：AU5516973A

公开(公告)日：1974-11-07

申请号：AU5516973

申请日：1973-05-03

Applicant: RCA CORP

Inventor： LIMBERG ALLEN LEROY

IPC: H04H20/89 ,  H04H5/00

Abstract: A 38kHz flag subcarrier accompanying an FM multiplex transmission identifies whether such multiplex transmission includes two channel or surround stereophonic information. Apparatus to provide such a flag subcarrier comprises, for example, a source of direct potential to unbalance a then unused balanced quadrature subchannel modulator within the transmitter during two channel transmission. Receiver apparatus to detect the transmission of such a flag subcarrier comprises a threshold detector coupled by a subsonic low pass filter to the corresponding synchronous subchannel detector. Indicating and/or automatic switching apparatus responsive to the detector output is provided.

公开(公告)号：DE2317124A1

公开(公告)日：1973-11-22

申请号：DE2317124

申请日：1973-04-05

Applicant: RCA CORP

Inventor： CHRISTENSEN ROY MARTIN ,  GIBSON JAMES JOHN ,  LIMBERG ALLEN LEROY

IPC: H04S3/02 ,  H04R5/04

公开(公告)号：GB1220955A

公开(公告)日：1971-01-27

申请号：GB2795768

申请日：1968-06-12

Applicant: RCA CORP

Inventor： LIMBERG ALLEN LEROY

IPC: H04N3/185 ,  H04N3/20 ,  H04N5/18 ,  H04N9/72

Abstract: 1,220,955. Video amplifiers; colour television receiver. R.C.A. CORPORATION. 12 June, 1968 [12 June, 1967], No. 27957/68. Headings H3T and H4F. Video amplifiers (e.g. transistors 36, 38, 40) which are A.C. coupled at 66, 68, 70 to the grids 60, 62, 64 of the tube 10 of a T.V. receiver and which have associated D.C. restoring diodes 76, 78, 80 arranged to conduct during retrace intervals, also have a protection circuit incorporating a further diode 102 which is connected between the restoring diodes and a potential source 88 and which is reverse biased by the source 88 during normal receiver operation. Each transistor 36, 38, 40 amplifies either a colour signal or a colour difference signal, the luminance signal in the latter case being applied to cathodes 16, 18, 20. A transistor switch 90 is turned on by line retrace signals 96 to earth collector 90 whereby the potential defined by a divider 84, 86 forward biases the restoring diodes 76, 78, 80 to discharge the capacitors 66, 68, 70 to the defined potential. If arc-over occurs in the tube 10 from high voltage to a grid 60, 62, 64, the protective diode 102 is forward biased and the arc-over surge current is discharged into the supply capacitor 104, thus protecting the transistors 36, 38, 40 from damage.

公开(公告)号：DE1234269B

公开(公告)日：1967-02-16

申请号：DER0034380

申请日：1963-02-05

Applicant: RCA CORP

Inventor： LIMBERG ALLEN LEROY

IPC: C07D231/56 ,  H03D1/22

Abstract: 1,000,229. Stereophonic radio signal receivers. RADIO CORPORATION OF AMERICA. Jan. 31, 1963 [Feb. 16, 1962], No. 4109/63. Heading H4L. In a compatible stereophonic receiver, for use with the standard U.S. stereophonic transmission system, de-emphasis of the subcarrier sideband signals is effected before demodulation. The receiver comprises an antenna 6 feeding signals through R.F. amplifier 5 and IF amplifier 7 to FM detector 8. The output signals from detector 8 are (L+R), a 19 kc/s. pilot signal and subcarrier sidebands representative of (L - R) with a centre frequency of 38 kc/s. These signals are fed over an amplifier 23 to an amplifier tube 18. The anode circuit of tube 18 is tuned to the pilot signal and is transformer coupled to a full wave rectification frequency doubling circuit 39. The output of circuit 39 (at the sub-carrier frequency of 38 kc/s.) is applied to a tube 48 in a modified Colpitts oscillator circuit 47. During monophonic reception tube 48 is biased to cut-off but when the pilot signal is present (i.e. during stereophonic transmission which is indicated by a neon lamp 33), the change in bias of tube 48 enables it to oscillate at 38 kc/s. (in synchronism with the pilot signal) thereby to re-insert the sub-carrier. A switching voltage at 38 kc/s. from oscillator 47 is coupled by windings 51 and 58 to a balanced synchronous peak detector circuit 57 operative to derive (L - R) from the sub-carrier sidebands. Winding 58 is connected to diodes 59 and 60 so that they conduct during the same part of the input cycle and the time constants of the resistor-capacitor networks 61-62 and 64-65 are chosen so that the conduction angle of the diodes is small. The subcarrier sidebands are applied at the centre tap of winding 58- having been selected from the cathode of amplifier tube 18 by a combined filter and deemphasis network 66. This network comprises a series resistor 67, shunt inductor 68 and a trap circuit with inductor 69 and capacitor 70 which are series resonant at 67 kc/s. The inductor 68 resonates at 38 kc/s. and attenuates signals on either side of this frequency. The overall characteristics of the network are such that high frequencies of the resultant demodulated signals are attenuated at approximately a rate of 75 Á sec. to provide the necessary high frequency de-emphasis. Demodulated (L - R) signals are developed across the output capacitor 63 of circuit 57 and applied to the tube 74 connected as a phase splitter so that a pair of series connected resistors 79 and 80 are coupled to receive opposite phases of L - R). The (L+R) signal is applied to the junction of resistors 79 and 80 via series resistors 85 and 86 and shunt capacitors 87 and 88 which serve to select the (L + R) signal from the cathode of tube 18 and provide deemphasis. The resultant L and R signals appear at output terminals 16 and 17 respectively. Specification 1,000,228 is referred to.