公开(公告)号：JP2006236424A

公开(公告)日：2006-09-07

申请号：JP2005046373

申请日：2005-02-23

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJIWARA ICHIRO ,  OKA OSAMU

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To realize preventing disturbance of a nonvolatile cell to which drain voltage of a selection cell is applied, with a method being suitable for low voltage operation. SOLUTION: The device has an operation circuit 9 for injecting electron injection and a non-selection word line bias circuit 9A as a function of a peripheral circuit. The operation circuit 9 controls operation injecting high energy electron charges to a local part of its lamination insulation film for data writing or erasing of a selected memory transistor to be operated. The non-selection word line bias circuit 9A applies the prescribed voltage to a non-selection memory transistor whose drain region is connected electrically to a drain region of the selected memory transistor through a nonvolatile word line in the direction where voltage between a drain and a gate is relaxed in injecting electron charges. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了实现防止对施加选择单元的漏极电压的非易失性单元的干扰，适用于低电压操作的方法。 解决方案：该装置具有用于注入电子注入的操作电路9和作为外围电路的函数的非选择字线偏置电路9A。 操作电路9控制将高能电子电荷注入其层压绝缘膜的局部部分，以便对要操作的所选存储晶体管进行数据写入或擦除。 非选择字线偏置电路9A将规定的电压施加到非选择性存储晶体管，其漏极区域通过非易失性字线电连接到所选择的存储晶体管的漏极区域，漏极区域与漏极区域 注入电子时门很松弛。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005332924A

公开(公告)日：2005-12-02

申请号：JP2004149006

申请日：2004-05-19

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJIWARA ICHIRO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a memory of a discrete trap type where the required variation width of threshold voltage is secured even when dropping operation voltage, by improving charge retention characteristic and improving charge storage density.
SOLUTION: A charge storage film is formed between a channel forming area and a gate electrode (WL), and comprises a charge storage means made discrete within a plane facing the channel forming area and in the direction of a film thickness. The charge storage film has a first insulating film 23 having a large number of micro-conductive particles 22 becoming a first charge storage means buried inside, and a second insulating film 24 which comprises a carrier trap becoming a second charge storage means and which is formed on the first insulating film 23 e.g.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：为了提供即使在降低操作电压时也能够确保阈值电压的所需变化宽度，通过改善电荷保持特性并改善电荷存储密度的离散陷阱型的存储器。 解决方案：在沟道形成区域和栅电极（WL）之间形成电荷存储膜，并且包括在与沟道形成区域相对的平面内并且在膜厚度方向上离散的电荷存储装置。 电荷存储膜具有第一绝缘膜23，该第一绝缘膜23具有多个微导电颗粒22，其成为埋入其中的第一电荷存储装置;以及第二绝缘膜24，其包括形成为第二电荷存储装置的载流子阱，并形成 在第一绝缘膜23上 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2005005513A

公开(公告)日：2005-01-06

申请号：JP2003167832

申请日：2003-06-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJIWARA ICHIRO ,  NAKAGAWARA AKIRA

IPC: G11C16/02 ,  G11C16/04 ,  G11C16/26 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC classification number: H01L27/11568 ,  G11C16/0475 ,  G11C16/0491 ,  G11C16/26 ,  H01L27/115 ,  H01L27/11521

Abstract: PROBLEM TO BE SOLVED: To provide a nonvolatile semiconductor memory of a structure enabling highly sensitive read operation at a lower voltage, and also to provide a method of the reading. SOLUTION: A gate insulating film GD is formed of a bottom insulating film BTM, a charge accumulating film CHS, and a top insulating film TOP sequentially from the lower side. The bottom insulating film BTM includes a nitride silicon oxide film SiON immediately under the charge accumulating film CHS. Bit information stored at a local area in the side of the sub-source line SSL of a memory transistor and bit information accumulated at a local area in the side of sub-bit line are read independently by a so-called reverse read method. Because of the existence of SiON, an incubation time is controlled, and thereby the film thickness controllability of the charge accumulating film CHS is improved. Moreover, since a threshold voltage under an erasing condition is lowered, low voltage operation and operation reliability can be improved in combination with the highly sensitive read operation. COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：提供一种能够在较低电压下进行高灵敏度读取操作的结构的非易失性半导体存储器，并且还提供读取方法。 解决方案：栅极绝缘膜GD从底部顺序地由底部绝缘膜BTM，电荷累积膜CHS和顶部绝缘膜TOP形成。 底部绝缘膜BTM包括在电荷蓄积膜CHS正下方的氮化硅氧化物膜SiON。 存储在存储晶体管的子源线SSL侧的局部区域的位信息和在子位线侧的局部区域累积的位信息通过所谓的反向读取方法独立地读取。 由于存在SiON，所以控制了孵育时间，从而提高了电荷蓄积膜CHS的膜厚可控性。 此外，由于在擦除条件下的阈值电压降低，所以与高灵敏度读取操作相结合可以提高低电压操作和操作可靠性。 版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004280965A

公开(公告)日：2004-10-07

申请号：JP2003072080

申请日：2003-03-17

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJIWARA ICHIRO ,  NAKAGAWARA AKIRA

IPC: G11C16/04 ,  G11C16/02 ,  G11C16/06 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To securely read data at a high speed in a nonvolatile semiconductor memory device having a non-conductive trap gate. SOLUTION: Source/drain regions of cell transistor Mi and an adjacent cell transistor Mi-1 or Mi+1 are electrically connected in common by a column line SDLi or SDLi+1. Column selecting means (P/B1-P/B9)apply reference voltage (0V) to a selected column line, and set read-out voltage states (BL) to the other column lines. Data D of a plurality of bits are read simultaneously from a plurality of column lines being adjacent the column line to which the reference voltage (0V) is applied, but, at the time, since a current is not made to flow in a cell transistor (e.g. M3, M7) not to be read and not connected to the column line to which the reference voltage (0V) is applied, the data D can be surely read at high speed. COPYRIGHT: (C)2005,JPO&NCIPI

公开(公告)号：JP2003078051A

公开(公告)日：2003-03-14

申请号：JP2002186626

申请日：2002-06-26

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJIWARA ICHIRO

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To structure a memory transistor having a charge storage means suitable when made fine.
SOLUTION: This device has a first conductive semiconductor substrate SUB, a gate insulating film, and a gate electrode WL formed on the semiconductor substrate. The device is internally provided with the charge storage means and has a second conductive source area S and a drain area D formed on the surface area of the semiconductor substrate on one side and the other side of the gate electrode WL in the width direction. A source contact plug SC is formed on one terminal of the source area S orthogonal in the width direction of its gate electrode WL. A bit contact plug BC is formed on the other terminal of the drain area D orthogonal in the width direction of its gate electrode. A source line SL is electrically connected to the source contact plug SC, and a bit line BL is electrically connected to the bit contact plug BC.
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：构造具有在精细时适合的电荷存储装置的存储晶体管。 解决方案：该器件具有形成在半导体衬底上的第一导电半导体衬底SUB，栅极绝缘膜和栅电极WL。 该器件内部设置有电荷存储装置，并且具有形成在半导体衬底的表面区域上的第二导电源区域S和漏区域D，栅极电极WL的宽度方向的一侧和另一侧。 源极接触插头SC形成在源极区域S的在其栅极WL的宽度方向上正交的一个端子上。 在其栅极电极的宽度方向正交的漏极区域D的另一个端子上形成有位接触插头BC。 源极线SL电连接到源极接触插头SC，并且位线BL电连接到位接触插头BC。

公开(公告)号：JP2003068892A

公开(公告)日：2003-03-07

申请号：JP2001254458

申请日：2001-08-24

Applicant: Sony Corp ,  ソニー株式会社

Inventor： NOMOTO KAZUMASA ,  AOZASA HIROSHI ,  FUJIWARA ICHIRO ,  TANAKA NOBUFUMI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a method for manufacturing using conditions decided based on a parameter by newly proposing changing guidelines (parameter) of manufacturing conditions effective to improve a charge injection speed. SOLUTION: The method for manufacturing a nonvolatile semiconductor memory device comprises a step of forming a gate dielectric film having a plurality of dielectric films BTM, CS, and TOP including a charge storage film CS on a surface of a semiconductor CH formed with a channel. The method further comprises a step of forming the film CS having a step of deciding a lower limit value of an Si-H bond surface density in the storage film necessary to perform a desired charge injection speed under predetermined bias condition, a step of deciding a film forming condition (e.g. a gas flow ratio) in which the Si-H bond surface density becomes a lower limit value or more, and a step of forming the film CS according to decided film forming conditions.

Abstract translation: 要解决的问题：提供一种通过新提出有效提高电荷注入速度的制造条件的改变指南（参数），基于参数决定的条件的制造方法。 解决方案：用于制造非易失性半导体存储器件的方法包括在形成有沟道的半导体CHCH的表面上形成具有多个介电膜BTM，CS和TOP的栅电介质膜的步骤，该电介质膜包括电荷存储膜CS。 所述方法还包括形成所述薄膜CS的步骤，所述薄膜CS具有在预定偏压条件下确定执行所需电荷注入速度所需的存储薄膜中的Si-H键表面密度的下限值的步骤， Si-H键表面密度成为下限值以上的成膜条件（例如气体流量比），以及根据所决定的成膜条件形成膜CS的工序。

公开(公告)号：JP2003046002A

公开(公告)日：2003-02-14

申请号：JP2001226719

申请日：2001-07-26

Applicant: Sony Corp ,  ソニー株式会社

Inventor： FUJIWARA ICHIRO

IPC: G11C16/04 ,  G11C16/02 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To reduce the time of for the overall write operation cycle, including reading and erasure, and enhance affinity with a CMOS process for facilitating realization of a low-cost memory hybrid system LSI.
SOLUTION: The memory has channel-sharing MIS transistors and memory transistors, having a gate dielectric film GD1 composed of a plurality of laminated dielectrics, including charge-storing means dispersed therein. At writing, hot electrons HE generated near the boundary of the MIS transistor and the memory transistor are injected into the gate dielectric film GD1 from the source S side thereof (Fig. 8A). At erasing, hot holes HH1, HH2 generated at the drain D side are injected in a distribution region of electrons stored in the gate dielectric film GD1 from the drain D side (Fig. 8B).
COPYRIGHT: (C)2003,JPO

Abstract translation: 要解决的问题：为了减少整个写入操作周期（包括读取和擦除）的时间，并且增强与CMOS工艺的亲和性，以便于实现低成本存储器混合系统LSI。 解决方案：存储器具有沟道共享MIS晶体管和存储晶体管，其具有由多个层压电介质组成的栅介质膜GD1，其中分散有电荷存储装置。 在写入时，在MIS晶体管和存储晶体管的边界附近产生的热电子HE从其源极S侧注入到栅极电介质膜GD1中（图8A）。 在擦除时，在漏极D侧产生的热孔HH1，HH2从漏极D侧注入到存储在栅极电介质膜GD1中的电子的分布区域中（图8B）。

公开(公告)号：JPH11224908A

公开(公告)日：1999-08-17

申请号：JP12642398

申请日：1998-05-08

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO ,  HAYASHI YUTAKA

IPC: H01L21/8247 ,  B82B1/00 ,  G11C16/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To correct program disturbance characteristics of a nonvolatile semiconductor memory containing charge storage means which are discrete on a plane. SOLUTION: Gate electrodes of a plurality of memory elements M are connected with a plurality of word lines WL. The source or drain region is connected with common lines, such as bit lines BL or source lines SL that cross word lines WL, from which they are electrically insulated. When writing, there are provided a write inhibit voltage supply means 20 that supplies a reverse bias voltage to the source or the drain region of a memory element M21 connected with a selective word line WL1 via a common line BL2 and/or SL2, so that the region is reverse biased with respect to the channel formed region and a non-selective word line bias means 22 that supply reverse bias voltage to the channel formed region to the non-selective word line WL2.

公开(公告)号：JPH1140682A

公开(公告)日：1999-02-12

申请号：JP19447597

申请日：1997-07-18

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO ,  NAKAMURA AKIHIRO ,  AOZASA HIROSHI

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To reduce the data writing speed and voltage while maintaining and improving the charge holding characteristic. SOLUTION: A gate insulating film 6 interposed between a channel forming region 1a and a gate electrode 8 is formed by laminating a tunnel film 10, an intermediate film 12, and a top film 14 in this order from the bottom. The top film 14 is formed by laminating a plurality of insulating films (e.g. 14a and 14b), and the lowermost film 14a thereof is an oxide film. The intermediate film 12 is a silicon nitride film, etc., and the film thickness thereof is not larger than 5 nm. The tunnel film 10 may have a construction comprising an oxidized nitride film besides an oxide film. A transition layer with intermediate composition is interposed between the intermediate film 12 and the top film 14. Alternatively, there is a high concentration deep charge trap having a trap level greater than 2.0 eV near the interface between both of them.

公开(公告)号：JPH09265676A

公开(公告)日：1997-10-07

申请号：JP7293296

申请日：1996-03-27

Applicant: SONY CORP

Inventor： KAMEI TAKAHIRO ,  KOBAYASHI TAKESHI ,  TOMITA HIDEMI ,  FUJIWARA ICHIRO

IPC: C07F7/12 ,  C07F7/18 ,  C07F7/28 ,  G01N37/00 ,  G01Q60/46 ,  G01Q80/00 ,  G01Q90/00 ,  G11B9/06 ,  G11B9/14

Abstract: PROBLEM TO BE SOLVED: To improve travelling property and durability of a recording medium for information recording and reproducing by bringing a needle electrode into contact with a charge accumulating layer, by holding an amphiphilic compd. having a specified compsn. on the contact face with the needle electrode. SOLUTION: This recording medium 10 consists of a substrate 11 and a charge accumulating layer 13 having electron or hole traps. Recording or reproducing of information is performed by bringing a needle electrode into contact with the layer 13. In this recording medium, at least the contact surface with the needle electrode contains amphiphilic compd. expressed by formula I or formula II. In formula I and formula II, R, R', R" are hydrophobic groups selected from CH3 (CH2 )m -CH3 (CH2 )m C6 H4 -(CH2 )n , CF3 (CF2 )m -(CH2 )p . A, A' are hydrophilic groups selected from Si(OR )3 SiCl3 , Ti(OR )3 , COOH, OH, NH2 , and R , R are CH3 or C2 H5 .