公开(公告)号：DE10144700A1

公开(公告)日：2002-04-18

申请号：DE10144700

申请日：2001-09-11

Applicant: SONY CORP

Inventor： KOBAYASHI TOSHIO ,  MORIYA HIROYUKI ,  FUJIWARA ICHIRO

IPC: B82B1/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: A non-volatile semiconductor memory has a channel forming zone consisting of a semiconductor, a charge memory layer (6) with several stacked dielectric layers (6-1,2,3) and capable of storing charge. Two memory zones (6a,6b) have regions of the charge memory layer which overlap the two ends of the channel forming region, and a dielectric single-cell layer (4) contacts the channel forming region between the memory/storage regions. A control gate electrode (5) contacts the dielectric single-cell layer (4) and a memory gate electrode (7) contacts both memory regions and has regions which contact the memory regions which electrically inter-contact one another.

公开(公告)号：DE10295303T5

公开(公告)日：2004-09-23

申请号：DE10295303

申请日：2002-09-25

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO ,  NOBUKATA HIROMI

IPC: G11C16/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L29/423 ,  H01L29/792 ,  H01L29/788 ,  H01L21/8247 ,  H01L27/115

公开(公告)号：DE10295303B4

公开(公告)日：2017-07-13

申请号：DE10295303

申请日：2002-09-25

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO ,  NOBUKATA HIROMI

IPC: H01L27/11563 ,  G11C16/04 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/11573 ,  H01L27/11575 ,  H01L29/423 ,  H01L29/792

Abstract: Nichtflüchtige Halbleiterspeichervorrichtung, umfassend – einen Speichertransistor (M) und – Speicherperipherieschaltungen (2a bis 9) zur Steuerung eines Betriebs des Speichertransistors (M), wobei der Speichertransistor (M) umfasst: ein Halbleitersubstrat (SUB, W) eines ersten Leitfähigkeitstyps, einen Kanalbildungsbereich (CH) eines ersten Leitfähigkeitstyps, wobei der Kanalbildungsbereich in einem Oberflächenbereich des Halbleitersubstrats (SUB, W) eingestellt ist, einen ersten Source-/Drainbereich (S, SSL), der auf einer Seite des Kanalbildungsbereichs (CH) in dem Oberflächenbereich des Halbleitersubstrats (SUB, W) gebildet und mit den Speicherperipherieschaltungen (2a bis 9) elektrisch verbunden ist, einen zweiten Source-/Drainbereich (D, SBL), der auf der anderen Seite des Kanalbildungsbereichs (CH) in dem Oberflächenbereich des Halbleitersubstrats (SUB, W) gebildet und mit den Speicherperipherieschaltungen (2a bis 9) elektrisch verbunden ist, einen Ladungsspeicherfilm (GD), der zumindest auf dem Kanalbildungsbereich (CH) gebildet ist und der über eine Ladungsspeicherfähigkeit verfügt, und eine Gateelektrode (WL), die auf dem Ladungsspeicherfilm (GD) gebildet und mit den Speicherperipherieschaltungen (2a bis 9) elektrisch verbunden ist, dadurch gekennzeichnet, dass die Speicherperipherieschaltungen (2a bis 9) eine erste Spannung (Vd) erzeugen, die erzeugte erste Spannung (Vd) an den zweiten Source-/Drainbereich (D, SBL) unter Heranziehen eines Potentials des ersten Source-/Drainbereichs (S, SSL) als Referenz anlegen, eine erste Polaritätsspannung (Vg) und eine zweite Polaritätsspannung (Vwell) mit einer voneinander entgegengesetzten Polarität erzeugen, wobei eine Potentialdifferenz davon gleich einer zweiten Spannung (Vg-Vwell) ist, die erzeugte erste Polaritätsspannung (Vg) an die Gateelektrode (WL) anlegen, ...

公开(公告)号：DE10194678T1

公开(公告)日：2003-10-16

申请号：DE10194678

申请日：2001-10-25

Applicant: SONY CORP

Inventor： NOMOTO KAZUMASA ,  AOZASA HIROSHI ,  FUJIWARA ICHIRO ,  TANAKA SHINJI

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/318 ,  H01L21/762 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

Abstract: The memory device has a plurality of dielectric films including charge storage layers CS having a charge holding capability therein and stacked on an active region of a semiconductor SUB and electrodes G on the plurality of dielectric films. Each charge storage layer CS includes a first nitride film CS 1 made of silicon nitride or silicon oxynitride and a second nitride film CS 2 made of silicon nitride or silicon oxynitride and having a higher charge trap density than the first nitride film CS 1 . The first nitride film CS 1 is formed by chemical vapor deposition using a first gas which contains a first silicon-containing gas containing chlorine with a predetermined percent composition and a nitrogen-containing gas as starting materials. The second nitride film CS 2 is formed by chemical vapor deposition using a second gas which contains a second silicon-containing gas having a lower chlorine percent composition than the above predetermined percent composition and a nitrogen-containing gas as starting materials.

公开(公告)号：JP2003204000A

公开(公告)日：2003-07-18

申请号：JP2002003242

申请日：2002-01-10

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: G11C16/02 ,  G11C16/04 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To solve the problem that an FG-type NAND memory cell array, which is made fine, has potential interference between proximity cells and becomes unstable in operation due to malfunction, depending on the circumstances. SOLUTION: A laminated film MGD is laminated between a 1st conductivity- type semiconductor (P well W), where a channel of a memory transistor (M11a, etc.), is formed and a gate electrode (word line WL11, etc.), and formed of a plurality of dielectric film including charge storage means (carrier trap) which are made discrete in plane. A bias supply circuit (not illustrated) controls respective potentials of bit lines BLa, source lines SL, and word lines (WL11, etc.), and gates of select transistors SG11 and SG12 so that when a selected memory transistor is written or erased, a hole generated due to inter-band tunneling is impressed to the charge storage means of the selected memory transistor from both impurity regions S and D on the source-line aide and bit-line side. COPYRIGHT: (C)2003,JPO

公开(公告)号：JP2002217317A

公开(公告)日：2002-08-02

申请号：JP2001007885

申请日：2001-01-16

Applicant: SONY CORP

Inventor： TANAKA NOBUFUMI ,  FUJIWARA ICHIRO ,  AOZASA HIROSHI ,  NOMOTO KAZUMASA

IPC: C23C16/34 ,  H01L21/318 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To suppress dispersion on the structure of a memory element and on its characteristics by shortening the incubation time in the formation of a charge storage film which preventing the deterioration in the characteristics of the element. SOLUTION: A non-volatile semiconductor storage device has a plurality of dielectric films GD laminated on a semiconductor SUB and a gate electrode GE on the dielectric films GD. A plurality of the dielectric films GD contain a bottom dielectric film BTM on the semiconductor SUB and charge storage films CHS having charge storage capacity. In a process in which dielectrics constituting the charge storage films CHS are formed on the bottom dielectric film BTM, the dielectric (the first film CHS1) brought into contact with a boundary with at least the bottom dielectric film BTM in the dielectrics is formed by using atomic-layer deposition(ALD). Lattice consistency with a foundation surface is improved in the case of the formation of the charge storage films CHS in the charge storage films CHS formed in this manner, and the incubation time is shortened.

公开(公告)号：JP2002203917A

公开(公告)日：2002-07-19

申请号：JP2001100264

申请日：2001-03-30

Applicant: SONY CORP

Inventor： TANAKA NOBUFUMI ,  FUJIWARA ICHIRO ,  AOZASA HIROSHI ,  NOMOTO KAZUMASA

IPC: H01L21/8247 ,  H01L21/28 ,  H01L21/318 ,  H01L21/762 ,  H01L27/115 ,  H01L27/12 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To lower the operating voltage of a nonvolatile semiconductor storage device and/or to increase the operating speed of the device by improving the charge holding characteristic of the device and, in addition, to suppress the secular changes of the characteristics of the device. SOLUTION: This nonvolatile semiconductor storage device contains a charge storing layer CS having charge holding ability and has a plurality of dielectric films laminated upon the active area of a semiconductor SUB and an electrode G provided on the dielectric films. The charge storing layer CS includes a first nitride film CS1 composed of silicon nitride or silicon oxynitride and a second nitride film CS2 composed of silicon nitride or silicon oxynitride and has a higher charge trapping density than the first nitride film CS1 has.

公开(公告)号：JP2002164446A

公开(公告)日：2002-06-07

申请号：JP2000336774

申请日：2000-11-02

Applicant: SONY CORP

Inventor： KOBAYASHI TOSHIO ,  MORIYA HIROYUKI ,  FUJIWARA ICHIRO

IPC: B82B1/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  H01L21/336 ,  H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor memory having no loss of storage, high in electric charge injection efficiency and enabling parallel opera tion by VG cell array. SOLUTION: The non-volatile semiconductor memory is provided with channel formation areas Ch1a, Ch1b, Ch2 and a plurality of laminated dielectric films 6-1, 6-2, 6-3. The non-volatile semiconductor memory has a charge holding film 6 having charge holding ability, two storage parts 6a, 6b comprising the area of the charge holding film 6 overlapped on both ends Ch1a, Ch1b of the channel formation area, a single layer dielectric film 4 in contact with the channel formation area Ch2 between the storage parts 6a, 6b, a control gate electrode 5 in contact with the single layer dielectric film 4, and a memory gate electrode 7 electrically connecting the storage part and the contact part in contact with the storage parts 6a, 6b, respectively.

公开(公告)号：JP2001085547A

公开(公告)日：2001-03-30

申请号：JP26450599

申请日：1999-09-17

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: H01L21/8247 ,  B82B1/00 ,  G11C16/04 ,  G11C16/26 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To reduce off-leak current of an unselected memory transistor without decreasing the readout current of a selected memory transistor. SOLUTION: This semiconductor storage device is characterized by that memory transistors M11 to M22, each having a source region and a drain region formed at a surface part of a semiconductor across a channel forming region, a gate insulating film which is provided on the channel-forming region and includes a charge storage means, and a gate electrode on the gate insulating film are arranged in the word direction and the bit direction. Furthermore, this device has a forward bias voltage supply means (row bias circuit) 21, which supplies a forward bias voltage having a voltage value reducing an off-leak current from an unselected cell to the gate electrodes of the unselected memory transistors M12 and M22 among the memory transistors M11 to M22, in the direction of the forward bias to the channel formation region.

公开(公告)号：JP2000200842A

公开(公告)日：2000-07-18

申请号：JP6910199

申请日：1999-03-15

Applicant: SONY CORP

Inventor： FUJIWARA ICHIRO

IPC: H01L21/8247 ,  B82B1/00 ,  G11C16/02 ,  G11C16/04 ,  G11C16/10 ,  H01L21/28 ,  H01L27/115 ,  H01L29/423 ,  H01L29/51 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a memory cell of MONOS(Metal-Oxide-Nitride-Oxide Semiconductor) type or the like which can be lessened in operating voltage keeping its disturbance characteristics and writing speed high. SOLUTION: A gate insulating film 6 and a gate electrode 8 are laminated on a semiconductor channel forming region 1a provided onto the surface of a substrate, and a charge storage means (a carrier trap in a nitride film 12 and near to an interface with a top insulating film) which is dispersed in a two-dimensional manner in the gate insulating film 6 is provided. The gate insulating film 6 comprises an FN(Fowler Nordheim) tunnel film 10 which is larger in permittivity than a silicon oxide film and has FN electric conduction characteristics. Therefore, the gate insulating film 6 can be lessened in film thickness in terms of a silicon oxide film, and a memory cell of this constitution can be operated on an lower voltage. Furthermore, the memory cell can be more lessened in operating voltage by a method wherein a pull-up electrode is provided above the gate electrode 8 close to it through the intermediary of a dielectric film, a pull-up gate bias circuit through which a prescribed voltage is applied to the pull-up gate is provided, and the gate electrode 8 is raised up in voltage by capacitive coupling.