公开(公告)号：MY129513A

公开(公告)日：2007-04-30

申请号：MYPI20000149

申请日：2000-01-18

Applicant: SONY CORP

Inventor： MUKAI MIKIO ,  HAYASHI YUTAKA

IPC: H01L27/10 ,  H01L27/108 ,  H01L21/8242 ,  H01L27/12 ,  H01L29/772 ,  H01L29/861 ,  H01L29/88 ,  H01L29/94

Abstract: A MEMORY CELL WITH A STORED CHARGE ON ITS GATE COMPRISING: (A) A CHANNEL FORMING REGION (15), (B) A FIRST GATE (13) FORMED ON AN INSULATION LAYER (12) FORMED ON THE SURFACE OF THE CHANNEL FORMING REGION (15), THE FIRST GATE (13) AND THE CHANNEL FORMING REGION (15) FACING EACH OTHER THROUGH THE INSULATING LAYER (18), (C) A SECOND GATE (19) CAPACITIVELY COUPLED WITH THE FIRST GATE, (D) SOURCE/DRAIN REGIONS (16, 17) FORMED IN CONTACT WITH THE CHANNEL FORMING REGION (15), ONE SOURCE/DRAIN REGION (16, 17) BEING SPACED FROM THE OTHER, (E) A FIRST NON-LINEAR RESISTANCE ELEMENT (30) HAVING TWO ENDS, ONE END BEING CONNECTED TO THE FIRST GATE (13), AND (F) A SECOND NON-LINEAR RESISTANCE ELEMENT (33) COMPOSED OF THE FIRST GATE (13), THE INSULATION LAYER (18) AND EITHER THE CHANNEL-FORMING REGION (15) AND AT LEAST ONE OF THE SOURCE/DRAIN REGIONS (16, 17). (FIG. 1A)

公开(公告)号：DE19804568B4

公开(公告)日：2009-03-19

申请号：DE19804568

申请日：1998-02-05

Applicant: SONY CORP

Inventor： KOMATSU YASUTOSHI ,  HAYASHI YUTAKA

IPC: H01L27/06 ,  H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L23/58 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H03K17/687

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

公开(公告)号：DE69522412T2

公开(公告)日：2002-05-29

申请号：DE69522412

申请日：1995-11-09

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  YAMAGISHI MACHIO

IPC: G11C17/00 ,  G11C7/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28

Abstract: A rewritable nonvolatile semiconductor memory device having a plurality of memory cells which are electrically and reversably variable in threshold values and one pair of reference cells, provided for each predetermined number of memory cells, having the same cross-sectional structure as the memory cells, the pair of reference cells having written in them data of opposite phases, and, at the time of reading, the currents of the pair of reference cells being combined to produce a reference current and the data being determined by comparing this with the signal current of the memory cell.

公开(公告)号：DE69522412D1

公开(公告)日：2001-10-04

申请号：DE69522412

申请日：1995-11-09

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  YAMAGISHI MACHIO

IPC: G11C17/00 ,  G11C7/06 ,  G11C16/04 ,  G11C16/06 ,  G11C16/28

Abstract: A rewritable nonvolatile semiconductor memory device having a plurality of memory cells which are electrically and reversably variable in threshold values and one pair of reference cells, provided for each predetermined number of memory cells, having the same cross-sectional structure as the memory cells, the pair of reference cells having written in them data of opposite phases, and, at the time of reading, the currents of the pair of reference cells being combined to produce a reference current and the data being determined by comparing this with the signal current of the memory cell.

公开(公告)号：CA2306002A1

公开(公告)日：2000-10-26

申请号：CA2306002

申请日：2000-04-18

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  KOBAYASHI TOSHIO ,  MUKAI MIKIO

IPC: H01L27/10 ,  G11C11/405 ,  G11C11/407 ,  H01L27/085

Abstract: A semiconductor memory cell comprising a first transistor for readout, a second transistor for switching, and having a first region, a second region formed in a surface region of the first region, a third region formed in a surface region of the second region, a fourth region formed in a surface region of the first region and spaced from the second region, a fifth region formed in a surface region of the fourth region, and a gate region, wherein when the semiconductor memory cell is cut with a first imaginary perpendicular plane which is perpendicular to the extending direction of the gate region and passes through the center of the gate region, the second region and the fourth region in the vicinity of the gate region are nearly symmetrical with respect to a second imaginary perpendicular plane which is in parallel with the extending direction of the gate region and passes through the center of the gate region.

公开(公告)号：DE69328342D1

公开(公告)日：2000-05-18

申请号：DE69328342

申请日：1993-12-09

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  MATSUSHITA TAKESHI

IPC: G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  G11C11/40

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor (TR1) comprising a first semiconductor channel forming region (Ch1), first and second conductive regions (SC1, SC2) and a first conductive gate (G1); and a switching transistor (TR2) comprising a second semiconductor channel forming region (Ch2), third and fourth conductive regions (SC3, SC4) and a second conductive gate (G2); wherein said first conductive gate (G1) and said second conductive gate (G2) are connected to a first memory-cell-selection line (1ST LINE), said fourth conductive region (SC4) is connected to said first semiconductor channel forming region (Ch1), said third conductive region (SC3) is connected to a second memory-cell-selection line (2ND LINE), and said first conductive region (SC1) is connected to a read line (READ LINE).

公开(公告)号：DE69328342T2

公开(公告)日：2000-09-07

申请号：DE69328342

申请日：1993-12-09

Applicant: SONY CORP

Inventor： HAYASHI YUTAKA ,  MATSUSHITA TAKESHI

IPC: G11C11/405 ,  G11C11/404 ,  H01L21/8238 ,  H01L21/8242 ,  H01L27/092 ,  H01L27/108 ,  H01L29/786 ,  G11C11/40

Abstract: A semiconductor memory cell, or a semiconductor memory cell for ASICs, of the structure is provided which ensures stable transistor operation, which does not require a large-capacitance capacitor as required in conventional DRAMs, which ensures reliable reading and writing of information, that permits short-channel design, and that allows the cell area to be reduced. The semiconductor memory cell includes: an information storage transistor (TR1) comprising a first semiconductor channel forming region (Ch1), first and second conductive regions (SC1, SC2) and a first conductive gate (G1); and a switching transistor (TR2) comprising a second semiconductor channel forming region (Ch2), third and fourth conductive regions (SC3, SC4) and a second conductive gate (G2); wherein said first conductive gate (G1) and said second conductive gate (G2) are connected to a first memory-cell-selection line (1ST LINE), said fourth conductive region (SC4) is connected to said first semiconductor channel forming region (Ch1), said third conductive region (SC3) is connected to a second memory-cell-selection line (2ND LINE), and said first conductive region (SC1) is connected to a read line (READ LINE).

公开(公告)号：DE19804568A1

公开(公告)日：1998-08-13

申请号：DE19804568

申请日：1998-02-05

Applicant: SONY CORP

Inventor： KOMATSU YASUTOSHI ,  HAYASHI YUTAKA

IPC: H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L27/088 ,  H01L23/58

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.

公开(公告)号：GB2322003A

公开(公告)日：1998-08-12

申请号：GB9802209

申请日：1998-02-02

Applicant: SONY CORP

Inventor： KOMATSU YASUTOSHI ,  HAYASHI YUTAKA

IPC: H01L21/336 ,  H01L21/84 ,  H01L29/78 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H01L29/423

Abstract: An IGFET, which may be in the form of a thin film transistor, has a bias element 30 and a capacitive element 40. A potentiual for controlling the gate threshold voltage is applied to the bias element whilst a signal of the same phase is supplied to the capacitive element. The bias element is either directly adjacent to the channel region or in the form of an additional second gate (figure 12A).

公开(公告)号：DE19804568B9

公开(公告)日：2009-08-06

申请号：DE19804568

申请日：1998-02-05

Applicant: SONY CORP

Inventor： KOMATSU YASUTOSHI ,  HAYASHI YUTAKA

IPC: H01L27/06 ,  H01L29/78 ,  H01L21/336 ,  H01L21/84 ,  H01L23/58 ,  H01L27/02 ,  H01L27/12 ,  H01L29/10 ,  H01L29/786 ,  H03K17/687

Abstract: An insulated-gate field effect transistor comprising a channel forming region, source/drain regions, a gate region, a bias supplying means, and a capacitive element, wherein a potential for controlling a gate threshold voltage of the insulated-gate field effect transistor in an off-state thereof is applied to the channel forming region through the bias supplying means, and a signal having approximately the same phase as a phase of a signal supplied to the gate region is supplied to the channel forming region through the capacitive element.