公开(公告)号：JPH0527191B2

公开(公告)日：1993-04-20

申请号：JP10968783

申请日：1983-06-18

Applicant: SONY CORP

Inventor： HIMENO TAKUJI

IPC: G11B20/10 ,  G11B27/36

公开(公告)号：JPH04321959A

公开(公告)日：1992-11-11

申请号：JP11933391

申请日：1991-04-22

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  HIMENO TAKUJI

IPC: G11B15/087 ,  G11B27/10 ,  G11B27/22 ,  G11B27/28 ,  G11B27/30

Abstract: PURPOSE:To improve the use convenience of a user at the time of program search processing by comparing an audio signal with plural threshold levels, and recording melody non-existence information and melody existence information obtained in accordance with a result of comparison together with the signal. CONSTITUTION:An inputted audio signal S1 is compared with plural threshold levels VR1-VR4 being different from each other, and when it is below the minimum level VR4, melody non-existence information is generated. On the other hand, when the audio signal S1 is above any level VR1-VR4, melody existence information containing its level is generated, and the melody non-existence information or the melody existence information is recorded onto a recording medium 1 together with the audio signal S1, therefore, the melody non-existence and the melody existence information can be recorded surely irrespective of the audio signal level. Also, at the time of reproduction, by comparing the set input threshold level and the reproducing threshold level of melody existence information, a melody existence part is retrieved, therefore, in accordance with the audio signal, the melody existence part can be retrieved.

公开(公告)号：JPH0446017B2

公开(公告)日：1992-07-28

申请号：JP10869783

申请日：1983-06-17

Applicant: SONY CORP

Inventor： TANAKA MASATO ,  HIMENO TAKUJI

IPC: H03M5/04 ,  G11B20/14 ,  H03M5/14 ,  H04L25/49

公开(公告)号：JPS63245023A

公开(公告)日：1988-10-12

申请号：JP7778387

申请日：1987-03-31

Applicant: SONY CORP

Inventor： SAKO YOICHIRO ,  HIMENO TAKUJI

IPC: H03M13/27

Abstract: PURPOSE:To prevent the deterioration the burst error correction length by expanding the final interleave interval of the P series and reversing the direction of retarding the interleave so as to locate the final word of the Q series after the preceding word. CONSTITUTION:The final interleave interval of the P series is expanded as to the P and Q series with respect to an optional word and the interleaving is applied to restore a word W7 and the Q series in reverse direction so as to locate the final word of the Q series after the recording word. Thus, even if an error exceeding the correctable burst error length takes place, the remaining error is reduced. Moreover, in order to improve the error correction capability at the simultaneous occurrence of a burst error and a random error, it is preferred to take the largest interleave delay quantity (quantity of restoration) in the reverse direction. Thus, the deterioration in the burst error correction capability is prevented and the deterioration in general error correction capability is prevented.

公开(公告)号：JPS63245022A

公开(公告)日：1988-10-12

申请号：JP7778287

申请日：1987-03-31

Applicant: SONY CORP

Inventor： SAKO YOICHIRO ,  HIMENO TAKUJI

IPC: G11B20/18 ,  H03M13/27 ,  H04B14/04

Abstract: PURPOSE:To prevent the reduction in the error correction capability by setting the interleave interval of an error correction code series longer partially to evade any word of P and Q series with respect to a prescribed object work from being duplicated in the recording direction. CONSTITUTION:The interleave interval of the error correction code series is set longer partially so as to evade the duplication in the recording direction as to words W0-W7 of the P and Q series with respect to the optional object word. Thus, even when the interleave interval is taken sufficiently large due to a small block size, the same frame except the object word is avoided as to each word of each error correction code system with respect to an optional object word. Thus, the reduction in the error correction capability is prevented.

公开(公告)号：JPS6313520A

公开(公告)日：1988-01-20

申请号：JP15730286

申请日：1986-07-04

Applicant: SONY CORP

Inventor： HIMENO TAKUJI

IPC: H03M1/20

Abstract: PURPOSE:To improve the conversion accuracy by holding the voltage of a capacitor at a time synchronously with a prescribed clock after an integration voltage reaches a prescribed voltage by means of a sample and holding circuit and adding an output of the sample and holding circuit to an input signal of the next sampling period. CONSTITUTION:The AD conversion section 10 is provided with a capacitor 2 receiving an analog input signal from an input terminal 1 at a prescribed period of sampling and a current source 3 to integrate the voltage, and the counting operation of a counter 5 is stopped just after the integration output exceeds the threshold value of a comparator 4. The voltage change by integration is quantized by turning off a switch SW3 of the current source 3 synchronously with the first cock after the integration output exceeds a prescribed threshold value of the comparator 4 and a difference from the analog input voltage is held in the capacitor 2. The error voltage is stored in a capacitor 21 of the sample and holding circuit 20, added to the input signal of the next sampling period and the added signal is used as the next AD conversion input. Thus, the quantization error is fed back.

公开(公告)号：JPS601676A

公开(公告)日：1985-01-07

申请号：JP10886783

申请日：1983-06-17

Applicant: SONY CORP

Inventor： HIMENO TAKUJI

IPC: G11B20/18

Abstract: PURPOSE:To detect assuredly an error of a data word by considering all words of a block containing words with which the errors are detected at a time as erroneous by the error check codes obtained from plural series of different data blocks of a prescribed number of data words. CONSTITUTION:A data block formed with a prescribed number of data words D1, D2-, the P- and Q-series parity check codes P and Q different from the data block series, a cyclic redundancy check code C of said block series, etc. When the errors of words D1, D2- which cannot be detected by the code C are detected by the codes P and Q, flags F1-F4 for P and Q series of wrong words D1, D2- are all set at ''1''. At the same time, the all flags of other words D1, D2- of the corresponding block are also set at ''1'' and considered as erroneous. Thus it is possible to detect a word error with no overlooking.

公开(公告)号：JP2010020387A

公开(公告)日：2010-01-28

申请号：JP2008177846

申请日：2008-07-08

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KOGANEZAWA TOMOHIRO ,  SHIMOYAMA TAKESHI ,  KOYAMA KINGO ,  HIMENO TAKUJI

IPC: G06F12/00

CPC classification number: H04N5/232 ,  G06F13/1689 ,  H04N5/23245

Abstract: PROBLEM TO BE SOLVED: To extremely reduce influence with frequency change processing concerning an apparatus mounting a memory for transferring data at high speed. SOLUTION: An arrow c1 for connecting an FCS 22, a CPU 21, a memory controller 23, a DDR-PHY controller 25, and a clock controller 26 is a signal for requesting frequency changeover. An arrow c2 is a signal for inputting a Self Refresh Enter command. Consequently, an LPDDRSDRAM 29 is operated in a self refresh mode. An arrow c4 is a signal for requesting the reset of DDR-PHY 24. An arrow c6 is a signal for requesting clock frequency changeover. An arrow c8 is a signal for requesting parameter setting of DDR-PHY, thereby selecting a DLL or a DL mounted on the DDR-PHY 24 as the one to be used, and determining a parameter to be set, etc. An arrow c10 is a signal for inputting a Self Refresh Exit command. An arrow c12 is a signal for announcing termination which expresses the termination of the frequency changeover. COPYRIGHT: (C)2010,JPO&INPIT

Abstract translation: 要解决的问题：为了极大地减少对安装用于高速传送数据的存储器的装置的频率变化处理的影响。 解决方案：用于连接FCS22，CPU21，存储器控制器23，DDR-PHY控制器25和时钟控制器26的箭头c1是用于请求频率切换的信号。 箭头c2是用于输入自刷新输入命令的信号。 因此，LPDDRSDRAM 29在自刷新模式下操作。 箭头c4是用于请求DDR-PHY24的复位的信号。箭头c6是用于请求时钟频率切换的信号。 箭头c8是用于请求DDR-PHY的参数设置的信号，从而选择安装在DDR-PHY 24上的DLL或DL作为要使用的信号，并确定要设置的参数等。箭头c10是 用于输入自刷新退出命令的信号。 箭头c12是表示终止频率切换的用于通知终止的信号。 版权所有（C）2010，JPO＆INPIT

公开(公告)号：JP2005063178A

公开(公告)日：2005-03-10

申请号：JP2003293021

申请日：2003-08-13

Applicant: Sony Corp ,  ソニー株式会社

Inventor： TANKI HIDEKAZU ,  HIMENO TAKUJI

IPC: G06F17/50

Abstract: PROBLEM TO BE SOLVED: To verify whether or not the behavior of a data processing system complies with a requested specification by expressing the function of the data processing system on a computer based on a calculation model, and providing the calculation model of the level of abstraction, that is a UT level, with a time concept in the case of developing the data processing system such as an LSI.
SOLUTION: This device 1 comprises: a test vector part 10 which provides a test vector having start time information, verification data column and an end sign; a first functional block model part 24 and a second functional block model part 27 which have a calculation model for describing the data processing system to process it according to the model; a first scheduled model part 23 and a second scheduled model part 26 which input the test vector applied from the test vector part 10 and manage the operation start time of the first functional block model part 24 and the second functional block model part 27 by referring to the start time included in the test vector; and a scheduler model part 21 which manages the scheduled model parts 23 and 26.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过基于计算模型在计算机上表达数据处理系统的功能来验证数据处理系统的行为是否符合所请求的规范，并且提供计算模型 在开发诸如LSI的数据处理系统的情况下具有时间概念的抽象级别，即UT级别。 解决方案：该装置1包括：测试向量部分10，其提供具有开始时间信息，验证数据列和结束符号的测试向量; 具有用于描述根据该模型处理它的数据处理系统的计算模型的第一功能块模型部分24和第二功能块模型部分27; 第一预定模型部分23和第二计划模型部分26，其输入从测试向量部分10应用的测试向量，并通过参考第一功能块模型部分24和第二功能块模型部分27来管理第一功能块模型部分24和第二功能块模型部分27的操作开始时间 开始时间包括在测试向量中; 以及调度模块部分21，其管理所计划的模型部分23和26.版权所有（C）2005，JPO＆NCIPI

公开(公告)号：JP2004303274A

公开(公告)日：2004-10-28

申请号：JP2004204485

申请日：2004-07-12

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HIMENO TAKUJI

IPC: G06F12/00 ,  G06F12/02 ,  G11B20/10 ,  G11B20/12

CPC classification number: Y02D10/13

Abstract: PROBLEM TO BE SOLVED: To realize power saving and noise reduction and the like by reducing the number of access time to row addresses and reducing transient of an address terminal.
SOLUTION: In continuously accessing respective column addresses which are a plurality of column addresses for one row address by using a predetermined number of bits of a column address as an access method for memory in which line addresses and column addresses are multiplexed, bit of a column address to be accessed at the first time is made to be have an equal value as a bit of a row address to be feeded to a same terminal.
COPYRIGHT: (C)2005,JPO&NCIPI

Abstract translation: 要解决的问题：通过减少对行地址的访问时间的数量和减少地址终端的瞬变来实现功率节省和降噪等。 解决方案：通过使用列地址的预定数量的比特作为存储器的访问方法，连续访问作为一行地址的多个列地址的各列地址，其中行地址和列地址被复用，存储器的位 将要首次访问的列地址作为要提供给同一终端的行地址的位具有相等的值。 版权所有（C）2005，JPO＆NCIPI