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公开(公告)号：JPH0954761A
公开(公告)日：1997-02-25
申请号：JP23074395
申请日：1995-08-15
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI , IWASE SEIICHIRO , YAMAZAKI TAKAO , NAKAMURA KENICHIRO
IPC: G06F15/80 , G06F15/78 , G06F15/167
Abstract: PROBLEM TO BE SOLVED: To attain a high programmability to high-rate signals including images by placing the controllers on the same silicon chip as that of the processor element groups in order to control in common the processor elements which construct the processor element groups. SOLUTION: A digital signal processor 1 contains the processor blocks 2A and 2B. These processors 2A and 2B are provided with the groups of processor elements PE including the elements PE in a number larger than the number of pieces of a series of serial data and having the multi-port memories RF and the arithmetic/logic units ALU which process each of a series of serial data. Then, the control circuits 3A, 3B, 3C and 3D which control in common the elements PE constructing the processor element groups are placed on the same silicon chip as that of these element groups. In such a constitution, the high programmability is attained.
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公开(公告)号：JPH08235129A
公开(公告)日：1996-09-13
申请号：JP3744495
申请日：1995-02-27
Applicant: SONY CORP
Inventor： OKI MITSUHARU , KUROKAWA MASUYOSHI
Abstract: PURPOSE: To efficiently perform multiplication with grouped filters whose coefficient values are not 0 like a filter used for a ghost canceler. CONSTITUTION: For data which are inputted at a sufficient interval of time, plural serial/parallel converters 1-3 are shifted in timing and then the passing and receiving time of the data is shortened by bringing necessary data to respective processor elements 4(j) or nearby processor elements 4(j) without passing and receiving the data to and from adjacent processor elements 4(j), thereby ending computation within one horizontal period. Namely, serial/parallel conversion is performed in different timing.
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公开(公告)号：JPH0863585A
公开(公告)日：1996-03-08
申请号：JP19662094
申请日：1994-08-22
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PURPOSE: To provide a parallel processor in which configuration is simplified as much as possible so as to suppress the increase of a circuit scale while improving processing capacity by parallel arithmetic processing. CONSTITUTION: A video editing device 1 is the parallel processor of what people call an SIMD system in which n-pieces (1
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公开(公告)号：JPH03249794A
公开(公告)日：1991-11-07
申请号：JP4863990
申请日：1990-02-28
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PURPOSE:To execute the fault diagnosis of a memory, etc., and the detection of a fault part by a host computer by providing a control part for generating a load signal to a register by a request from the host computer. CONSTITUTION:The circuit is provided with a control part 11 for monitoring a blanking signal and generating a load signal to a register 9 by a request from a host computer. The host computer, first of all, writes prescribed data in a specific address of an image memory, and sets the specific address to an address register 12. To other address than said address of the image memory, other code which can be discriminated from this code is set. In such a state, in a blanking period, the load signal is supplied to the register 9, and the register 9 inputs data of the specific address. When the contents of this register 9 are read out by the host computer, whether the set code is obtained or not is decided. In such a way, a fault part can be detected easily.
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公开(公告)号：JP2014103543A
公开(公告)日：2014-06-05
申请号：JP2012254407
申请日：2012-11-20
Inventor： UEKI NOBUO , KUROKAWA MASUYOSHI , YAGASAKI YOICHI , AOKI MAKOTO
CPC classification number: H04N5/2351 , H04N3/155 , H04N5/232 , H04N5/23235 , H04N5/335 , H04N5/357 , H04N5/3698 , H04N5/378 , H04N19/107 , H04N19/117 , H04N19/12 , H04N19/124 , H04N19/13 , H04N19/136 , H04N19/146 , H04N19/44 , H04N19/52 , H04N19/59 , H04N19/593 , H04N19/625 , H04N19/86
Abstract: PROBLEM TO BE SOLVED: To enable improvement in imaging performance.SOLUTION: An image sensor comprises: a light receiving unit that receives incident light and performs photoelectric conversion; and a compression unit that compresses image data obtained in the light receiving unit. An imaging device comprises: an image sensor having a light receiving unit that receives incident light and performs photoelectric conversion, and a compression unit that compresses image data obtained in the light receiving unit; and a decompression unit that decompresses coded data which is output from the image sensor, and is obtained through compression of the image data by the compression unit.
Abstract translation: 要解决的问题：能够提高成像性能。解决方案：图像传感器包括：光接收单元，其接收入射光并执行光电转换; 以及压缩单元，压缩在光接收单元中获得的图像数据。 一种成像装置，包括：具有接收入射光并进行光电转换的光接收单元的图像传感器，以及压缩单元，压缩在所述光接收单元中获得的图像数据; 以及解压缩单元，其对从图像传感器输出的编码数据进行解压缩，并且通过压缩单元压缩图像数据而获得。
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Patent Agency Ranking46.发明专利Video/sound setting information management device, processing method therefor, and program 有权视频/声音设置信息管理设备，其处理方法和程序
公开(公告)号：JP2009100123A
公开(公告)日：2009-05-07
申请号：JP2007268203
申请日：2007-10-15
Inventor： XAVIER MICHEL , UEDA KAZUHIKO , KUROKAWA MASUYOSHI , AOYAMA KOJI
CPC classification number: H04N7/163 , H04N21/26606 , H04N21/4405 , H04N21/4532 , H04N21/4623 , H04N21/4627 , H04N21/47
Abstract: PROBLEM TO BE SOLVED: To share settings that matches the preference of respective persons with respect to adjustment items of a video/sound presenting device to recommend settings according to conditions on the basis of the settings.
SOLUTION: Setting information about display of a video signal or output of a sound signal is held in a setting information database 210 in association with a viewing condition for them. A setting information registration part 230 registers the setting information and a viewing condition for it, which are accepted by a setting information acceptance part 220, so that they are held in the setting information database 210. A validity decision part 240 makes decision about the validity of recommended setting information which will be registered with the setting information database 210. A condition extraction part 260 extracts setting information registered with the setting information database 210, on the basis of a viewing condition supplied from an extracted condition acceptance part 250. A recommended setting deriving part 270 derives recommended setting information from extracted setting information on the basis of the extraction results of the condition extraction part 260.
COPYRIGHT: (C)2009,JPO&INPITAbstract translation: 要解决的问题：为了分享与视频/声音呈现设备的调整项目相关的人的偏好的设置，以根据设置的条件来推荐设置。 解决方案：将关于视频信号的显示或声音信号的输出的信息与关于它们的观看条件相关联地保存在设置信息数据库210中。 设置信息登记部分230登记设置信息及其设置信息接收部分220接受的查看条件，使得它们被保存在设置信息数据库210中。有效性决定部分240对有效性作出决定 推荐设置信息将被设置信息数据库210注册。条件提取部分260基于从提取条件接收部分250提供的观看条件，提取登记在设置信息数据库210中的设置信息。推荐设置 派生部分270根据条件提取部分260的提取结果从提取的设置信息中导出推荐的设置信息。（C）版权所有：（C）2009，JPO＆INPIT
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公开(公告)号：JP2005286491A
公开(公告)日：2005-10-13
申请号：JP2004094790
申请日：2004-03-29
Inventor： XAVIER MICHEL , NISHIBORI KAZUHIKO , AOYAMA KOJI , KUROKAWA MASUYOSHI
CPC classification number: G06T7/223
Abstract: PROBLEM TO BE SOLVED: To provide a technology of enhancing image quality in motion correcting image processing utilizing a motion vector by suppressing the distortion of an image generated by interpolation caused in the unit of a block and mismatching between a pixel generated by the interpolation and its surrounding pixels while reducing the cost of computational complexity. SOLUTION: An inter-field interpolation space transition is obtained on the basis of difference absolute sums between an inter-field interpolation pixel Pt and a pixel B adjacent to the pixel Pt on the same field and between the inter-field interpolation pixel Pt and a pixel D adjacent to the pixel Pt on the same field. An inter-field interpolation time transition is obtained on the basis of difference absolute sums between the inter-field interpolation pixel Pt and a pixel A at the same position in a preceding delayed field and between the inter-field interpolation pixel Pt and a pixel C at the same position in a present field. An in-field interpolation time transition is obtained on the basis of difference absolute sums between an in-field interpolation pixel Ps and the pixel A at the same position in the preceding delayed field and between the in-field interpolation pixel Ps and the pixel C at the same position in the present field. An amount of errors produced in pixels generated by the interpolation is obtained on the basis of the information of the inter-field interpolation space transition, the inter-field interpolation time transition, and the in-field interpolation time transition, and the inter-field interpolation or the in-field interpolation is selected depending on the amount of generated errors to generate pixels. COPYRIGHT: (C)2006,JPO&NCIPI
Abstract translation: 要解决的问题：提供一种利用运动矢量来提高运动校正图像处理中的图像质量的技术，该技术通过抑制以块为单位产生的内插产生的图像的失真和由 插值及其周围像素，同时降低计算复杂度的成本。 解决方案：基于场间插值像素Pt和与同一场上的像素Pt相邻的像素B之间的差绝对和获得场间插值空间转换，并且在场间插值像素 Pt和与同一场上的像素Pt相邻的像素D. 基于场间内插像素Pt和先前延迟场中相同位置之间的像素A与场间插值像素Pt与像素C之间的差绝对值之和，获得场间插值时间转换 在现在的领域处于相同的位置。 基于场前插补像素Ps和前一延迟场中相同位置处的像素A之间的差绝对和和场内插值像素Ps与像素C之间的差异，获得场内插值时间转换 在现在的领域处于同一位置。 基于场间插值空间转换，场间插值时间转换和场内插值时间转换的信息，以及场间插值时间转换的信息，获得由内插产生的像素中产生的误差量 根据生成的像素的误差量来选择插值或场内插值。 版权所有（C）2006，JPO＆NCIPI
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公开(公告)号：JPH10333971A
公开(公告)日：1998-12-18
申请号：JP13833397
申请日：1997-05-28
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI
Abstract: PROBLEM TO BE SOLVED: To make it possible to use a memory as a line FIFO. SOLUTION: A write port conversion generation part 52 and a read port conversion generation part 53 execute the storage, addition and comparison of various values. An address modification circuit 55 executes the comparison, addition and selection of a value outputted from the generation part 52 and an address read out from a program memory and supplies a modified address to a data memory part 4. Similar operation is executed also by the generation part 53 and address modification circuits 56, 57. Outputs from the generation parts 52, 53 are supplied also to a flag generation circuit 54. In the case of writing or reading out data in/from the memory part 4, a flag is inspected.
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公开(公告)号：JPH10312454A
公开(公告)日：1998-11-24
申请号：JP12047497
申请日：1997-05-12
Applicant: SONY CORP
Inventor： KUROKAWA MASUYOSHI , IWASE SEIICHIRO
IPC: G06T1/20
Abstract: PROBLEM TO BE SOLVED: To process high speed data by paralelling clock frequency of data outside an LSI by polyphasing it and making interface with an LSI operation part. SOLUTION: A high speed processing is enabled in an SIMD(single instruction stream/multiple data stream), however, the high speed processing is difficult outside the LSI, therefore, the processing on a substrate is performed with a half frequency of the clock frequency of pixel data inputted in an input SAM part 22. And the pixel data of a clock with lower speed is synthesized by three state buffers 51, 52 in the LSI, supplied to the input SAM part 22 and processed at high speed. The data of a clock with high speed outputted from an output SAM part 25 is converted into the data of the clock with low speed again in a register in the LSI.
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公开(公告)号：JPH10243259A
公开(公告)日：1998-09-11
申请号：JP8129597
申请日：1997-03-31
Applicant: SONY CORP
Inventor： OKUDA TAKUSHI , KUROKAWA MASUYOSHI , IWASE SEIICHIRO
Abstract: PROBLEM TO BE SOLVED: To quickly display the processing result by designating the characteristics of non-linear processing to image data through a GUI. SOLUTION: A personal computer 72 displays a GUI image for input on a monitor. When a user designates non-linear characteristics through an input device 70 to the GUI image, the personal computer 72 extracts a diagonal line function, showing non-linear characteristics and displays it in the GUI image. Further, the personal computer 72 generates a program for a linear array type multi-parallel processor (DSP 80) to execute non-linear processing which is shown by the extracted diagonal function and downloads the generated program to the DSP 80.
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