公开(公告)号：JPH05144952A

公开(公告)日：1993-06-11

申请号：JP32962591

申请日：1991-11-20

Applicant: SONY CORP

Inventor： SHINOHARA KEIJI ,  SAITO MASAKI

IPC: H01L21/28 ,  H01L21/768 ,  H01L23/522

Abstract: PURPOSE:To realize good electrical and mechanical connection between a wiring of an upper layer of a wiring layer and a conductive material inside a connection hole by making a specified region of a layer insulating layer in a periphery of an opening part a high heating fluid region. CONSTITUTION:A layer insulating layer 12 is deposited on a silicon substrate 1 wherein a diffusion layer 10 is formed. Since phosphorus and boron do not elute to a region 12A which is coated with a resist 40, it becomes a high heating fluid region 14 and a region 12B which is not coated with a resist becomes a low heating fluid region 16. Then, the resist 40 is removed and an opening 18 is formed in the high heating fluid region 14. When the layer insulating layer 12 is heated, a taper 20 is applied to the layer insulating layer in a periphery of the opening part 18. Thereby, a contact area between a wiring 32 and a connection hole 24 is enlarged and good connection can be realized.

公开(公告)号：JP2006253267A

公开(公告)日：2006-09-21

申请号：JP2005065085

申请日：2005-03-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： HIRANO TOMOYUKI ,  SAITO MASAKI

IPC: H01L29/78 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To provide a method of manufacturing a semiconductor device which makes a gate insulation film of a material having a lower dielectric constant without increasing the interfacial level in an interface between a semiconductor substrate and the gate insulation film.
SOLUTION: The gate insulation film 102 of a silicon oxide-based material is formed on the semiconductor substrate 100. Then, a gate electrode layer 103 containing a metal material is formed on the gate insulation film 102. Thereafter, by diffusing the metal material from the gate electrode layer 103 to the gate insulation film 102 by heat treatment, a metal oxide silicon layer 102a is formed at least in a surface layer of the gate insulation film 102.
COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 解决的问题：提供一种制造半导体器件的方法，其制造具有较低介电常数的材料的栅极绝缘膜，而不增加半导体衬底和栅极绝缘膜之间的界面中的界面水平。 解决方案：在半导体衬底100上形成氧化硅基材料的栅极绝缘膜102.然后，在栅极绝缘膜102上形成含有金属材料的栅电极层103。 通过热处理从栅极电极层103到栅极绝缘膜102的金属材料，至少在栅极绝缘膜102的表面层形成金属氧化物硅层102a。（C）2006，JPO＆NCIPI

公开(公告)号：JP2002176053A

公开(公告)日：2002-06-21

申请号：JP2000370161

申请日：2000-12-05

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA ,  SAITO MASAKI

IPC: C01B21/068 ,  C23C16/34 ,  H01L21/31 ,  H01L21/318 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To manufacture a semiconductor device which comprises a nitride film and is high in any of an integration degree, a reliability and a performance, at low cost. SOLUTION: In a semiconductor device, a nitride film is formed of first and second materials not containing hydrogen. Therefore, a even though the nitride film is formed, the hydrogen is not diffused in a base body. As the activated first material is transferred on the base body by a diffusion or the pressure difference, the kinetic energy of the first material transferred on the base body is low and damage to the base body is little. Moreover, as the second neutral material is also transferred on the base body, the charge-up of the base body is little.

公开(公告)号：JPH1126724A

公开(公告)日：1999-01-29

申请号：JP18200297

申请日：1997-07-08

Applicant: SONY CORP

Inventor： SAITO MASAKI

IPC: H01L27/04 ,  H01L21/822 ,  H01L21/8242 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To enable filling of a capacitor with a void-free insulating film, and prevent damage to the capacitor due to gas expansion in a void and reduction in yield of a semiconductor device due the damage. SOLUTION: On a substrate 30 covered with a first polysilicon film 34 constituting a bottom part of a lower electrode of a cylinder capacitor, a silicon oxide film 35 having an impurity concentration gradually lowered from the bottom to the surface is formed. The silicon oxide film 35 is patterned by dry etching, thus forming a silicon oxide pattern 35a. An exposed surface of the silicon oxide pattern 35a is wet-etched, until the sidewall of the silicon oxide pattern 35a becomes substantially perpendicular to the surface of the substrate 30 and a native oxide on an exposed surface of the first polysilicon film 34 is removed. After that, a second polysilicon film constituting a lateral part of the lower electrode of the cylinder capacitor is formed on the substrate 30 in such a state as to cover the silicon oxide pattern 35a.

公开(公告)号：JPH10178009A

公开(公告)日：1998-06-30

申请号：JP33919996

申请日：1996-12-19

Applicant: SONY CORP

Inventor： SAITO MASAKI

IPC: H01L21/31 ,  H01L21/316

Abstract: PROBLEM TO BE SOLVED: To remove an organic substance on a substrate surface without generating an unwanted natural oxide film for a substrate surface, and with preventing residues caused by carbonizing the organic substance adsorbed to the substrate surface. SOLUTION: First, a silicon substrate is carried into a furnace and the silicon substrate is exposed to oxidizing gas introduced into the furnace, whereby an organic substance adsorbed to a substrate surface of a silicon substrate is burnt. At this time, in a state that an interior of the furnace is held in a temperature range from 200 deg.C to 400 deg.C, the substrate starts to be exposed to oxidizing gas. A specific process for the silicon substrate, for example a heat assisted CVD, is performed in the same furnace.

公开(公告)号：JPH098026A

公开(公告)日：1997-01-10

申请号：JP9317396

申请日：1996-03-22

Applicant: SONY CORP

Inventor： KURIHARA HISAAKI ,  SAITO MASAKI ,  KOUZUKI TAKAAKI

IPC: H01L23/52 ,  H01L21/316 ,  H01L21/3205 ,  H01L21/768

Abstract: PROBLEM TO BE SOLVED: To provide a method for forming an NSG film by means of O3 -TEOS having a small absolute difference in stages without increasing an entire amount. SOLUTION: A method for forming an NSG film comprises a first process (Fig. (a)) for performing oxygen plasma processing while performing thermal treatment on a substrate 22 with an aluminum interconnection layer 24 formed on a principle surface, a second process (Fig. (b)) for forming an SiO2 film 26 by means of plasma CVD on the principle surface with the aluminum interconnection layer formed, and further a third process (Fig. (c)) for forming a nondoped silicated glass (NSG) film 28 by means of O3 -TEOS. The first process is preferably performed under such conditions that a heating temperature of the substrate is in a range of 200 to 450 deg.C, a chamber pressure is in a range of 600 to 3000Pa, an oxygen gas flow rate is in a range of 400 to 2000sccm, and discharging output density on the substrate is in a range of 1.2 to 3.2W/cm .

公开(公告)号：JPH08203889A

公开(公告)日：1996-08-09

申请号：JP1210795

申请日：1995-01-27

Applicant: SONY CORP

Inventor： SAITO MASAKI

IPC: H01L21/316

Abstract: PURPOSE: To prevent organic compounds from being taken in without depositing any native oxide by carrying a substrate into an atmosphere of such conditions as depositing no oxide on the surface of the substrate, exposing the substrate to an oxidative gas at a predetermined temperature and then subjecting the substrate to predetermined processing. CONSTITUTION: A wafer, i.e., a silicon substrate having surface adsorbed with organic compounds, is set on a wafer board 3 in a load lock chamber which is then evacuated. While sustaining the temperature in the furnace at about 400 deg.C, the wafer board 3 is transferred from the load lock chamber into the furnace. Subsequently, the inside of the furnace is purged by introducing N2 gas and O2 gas is introduced at a flow rate of 10000sccm for 300min. Consequently, organic compounds can be removed without depositing any oxide on the surface of the silicon substrate. N2 gas is then introduced again and the temperature in the furnace is increased to 900 deg.C while purging the furnace. Finally, O2 is introduced into the furnace thus oxidizing the surface of the silicon substrate.

公开(公告)号：JPH08186107A

公开(公告)日：1996-07-16

申请号：JP33899594

申请日：1994-12-29

Applicant: SONY CORP

Inventor： AJISAWA HARUHIKO ,  ENOMOTO YASUYUKI ,  SAITO MASAKI

IPC: C30B25/14 ,  C23C16/44 ,  C23C16/455 ,  H01L21/205 ,  H01L21/316

Abstract: PURPOSE: To form a film in a uniform thickness when a thin film is formed on a board by a CVD method. CONSTITUTION: A film forming apparatus for a CVD comprises a plurality of gas supply ports 13a, 13b, 13c, 13d as at least first material gas supply port, and a gas head for injecting the gas from a slitlike gas injection port through the plurality of the gas supply ports, wherein the ports 13a, 13b, 13c, 13d of at least the first gas are so arranged that two or more do not exist in an arbitrary surface perpendicular to the longitudinal direction L of the gas injection port 18. Or, the ports 13a, 13b, 13c, 13d are arranged at an equal interval in the longitudinal direction L of the port 18. Or, the width of the gas channel from the upper parts of the ports 13a, 13b, 13c, 13d to the port 18 is gradually extended in the direction L of the injection port. Or, a plurality of the gas heads in which the forming positions of the ports 13a, 13b, 13c, 13d are different from each other are used.

公开(公告)号：JPH0774321A

公开(公告)日：1995-03-17

申请号：JP23890893

申请日：1993-08-31

Applicant: SONY CORP

Inventor： SAITO MASAKI

IPC: H01L21/316 ,  H01L21/318 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8247 ,  H01L27/04 ,  H01L27/10 ,  H01L27/108 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To improve film quality by preventing the adverse effect (problem of defective withstand voltage characteristics and poor oxidation resisting property of the initial film) inflicting on the silicon nitride film having the base layer of capacitor insulating film, and to obtain a capacitor of excellent characteristics. CONSTITUTION:In the method of manufacture of a capacitor which is constructed in such a manner that at least one-layer silicon oxide films 4 and 6 are placed between the first and the second electrodes 3 and 7 and also at least a layer of silicon nitride film 5 is positioned between the first and the second electrodes 3 and 7, a thermal nitrification treatment is conducted on the silicon nitride film 5 after formation of the silicon nitride film 5.

公开(公告)号：JPH06204486A

公开(公告)日：1994-07-22

申请号：JP34845692

申请日：1992-12-28

Applicant: SONY CORP

Inventor： SUGIYAMA HISANOBU ,  SAITO MASAKI

IPC: H01L21/8247 ,  H01L29/788 ,  H01L29/792

Abstract: PURPOSE:To uniform the data erasing characteristic of memory cells by ensuring that the silicon particle size of a polysilicon layer comprising a floating gate is equal to or larger than a specific multiple of the shorter size of the superposed area of the floating gate and a source region. CONSTITUTION:A floating gate structure is adopted, and a value of 2.5a or above is taken for the silicon particle size lambda where (a) is the shorter size of a data erasure region. With this size of the silicon particle, a silicon particle SG plane is considered flat. As a result the cross section of a silicon particle SG is rectangular at the boundary of a gate insulating film OX, and the probability that the boundary of a silicon particle SG will be located in the data erasure region is significantly reduced. This prevents the fluctuation in tunneling current of each memory cell and threshold voltage of a MOS diode, uniforms the data erasing characteristic, and requires no additional circuit to prevent excess charge emission. The condition of silicon particle size lambda>=2.5a is deduced from (gamma/2).(1-costheta)/a