公开(公告)号：JP2006261283A

公开(公告)日：2006-09-28

申请号：JP2005074665

申请日：2005-03-16

Applicant: Sony Corp ,  ソニー株式会社

Inventor： KATAOKA TOYOTAKA

IPC: H01L27/092 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/78

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device that mainly has tensile strain or compression strain only in channel direction, and to provide its manufacturing method. SOLUTION: Gate electrodes 22n and 22p are formed on a semiconductor substrate 1 with a gate insulating film 21 in-between. Semiconductor layers 4 and 5 made of a material whose lattice spacing is different from that of the semiconductor substrate 1 are embedded in the semiconductor substrate 1, in a manner to pinch a channel formation area beneath the gate electrodes 22n and 22p. Source and drain layers 26n and 26p are formed on the semiconductor substrate 1 and the semiconductor layers 4 and 5 on both sides of the gate electrodes 22n and 22p. COPYRIGHT: (C)2006,JPO&NCIPI

Abstract translation: 要解决的问题：提供主要仅在通道方向上具有拉伸应变或压缩应变的半导体器件，并提供其制造方法。 解决方案：栅电极22n和22p形成在半导体衬底1上，栅极绝缘膜21在其间。 由晶格间隔与半导体基板1的晶格间隔不同的材料制成的半导体层4和5以夹持栅电极22n和22p下方的沟道形成区域的方式埋设在半导体衬底1中。 源极和漏极层26n和26p形成在半导体衬底1上，并且在栅电极22n和22p的两侧形成半导体层4和5。 版权所有（C）2006，JPO＆NCIPI

公开(公告)号：JP2000340670A

公开(公告)日：2000-12-08

申请号：JP14656499

申请日：1999-05-26

Applicant: SONY CORP

Inventor： KASHIWAGI AKIHIDE ,  KATAOKA TOYOTAKA

IPC: H01L21/31 ,  H01L21/318 ,  H01L21/8234 ,  H01L21/8242 ,  H01L27/088 ,  H01L27/108

Abstract: PROBLEM TO BE SOLVED: To eliminate dry etching by forming an insulating film on the surface of a semiconductor layer and providing the insulating film with a first region and a second region composed of a substance having a dielectric constant different from that of a substance composing the first region. SOLUTION: A insulating film 26 having first and second regions 22, 23 is formed on the surface of a semiconductor layer 20. The first region 22 is formed of SiO2 and the second region 23 is formed of SiOxNy/SiO2. In other words, the second region 23 is composed of a substance having a dielectric constant higher than that of the first region 22. An insulating film 26 composed of the first region 22 functions as a gate insulating film for a transistor element constituting a memory whereas an insulating film 26 composed of the second region 23 functions as a gate insulating film for a transistor element constituting a logic circuit.

公开(公告)号：JP2000332005A

公开(公告)日：2000-11-30

申请号：JP14470599

申请日：1999-05-25

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA

IPC: H01L21/31 ,  H01L21/318

Abstract: PROBLEM TO BE SOLVED: To provide a plasma nitriding apparatus capable of controlling plasma density and controlling the energy of reactant kinds entering a semiconductor substrate independently, and capable of introducing nitrogen having a concentration as high as possible only into the surface of an insulating film. SOLUTION: A plasma nitriding apparatus for nitriding the surface of an oxide film comprises (A) a plasma-forming region 10A for forming nitrogen molecules or nitrogen molecule ions in excited states by having the nitrogen- family gas irradiated with electromagnetic waves and (B) a treatment chamber 10 having a plasma nitriding region 10B. A first electrode 20, to which a potential equal to or negative than the potential of the plasma forming region 10A, is applied and a second electrode 21 to which a potential positive than the potential of the first electrode 20 is applied, from the plasma forming region 10A side, are provided in the plasma nitriding region 10B.

公开(公告)号：JPH10313049A

公开(公告)日：1998-11-24

申请号：JP12222697

申请日：1997-05-13

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA

IPC: H01L21/76

Abstract: PROBLEM TO BE SOLVED: To provide a semiconductor device in which a microelement isolation region can be formed without using a method for burying an insulator in a groove or disturbing the microminiaturization of the element, and a method for manufacturing it. SOLUTION: An Si3 N4 film 3 in a prescribed shape is formed through a buffer oxide film 2 on an Si substrate 1, and the etching of the Si substrate 1 is carried out by using this Si3 N4 film 3 as a mask, and an element separation groove 5 is formed. Next, an epitaxial Si film 6 is selectively grown on the bottom face and inside wall of the element separation groove 5 by a selective epitaxial growing method by using the Si3 N4 film 3 as a mask, and then the epitaxial Si film 6 is oxidized by a thermal oxidization method, and an element isolation region 8 is formed.

公开(公告)号：JPH09260517A

公开(公告)日：1997-10-03

申请号：JP9062996

申请日：1996-03-19

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA

IPC: H01L21/8247 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

Abstract: PROBLEM TO BE SOLVED: To provide a non-volatile semiconductor storage device where erasing voltage is low and storage holding capacity is high. SOLUTION: An SiO2 film 33 being a tunnel insulating film, a P-type polycrystalline Si film 34, an N-type polycrystalline Si film 35, an SiO2 film 36 being an insulating film for capacitive coupling and a tungsten polycide layer 41 being a gate electrode are sequentially stacked on an Si substrate 31. Electrons accumulated in the polycrystalline Si film 35 are not discharged to the Si substrate 31 through the SiO2 film 33 even if the SiO2 film 33 is such a thin one that tunneling can directly be executed owing to a potential barrier by means of P-N junction between the polycrystalline Si films 34 and 35 and even if voltage is not applied to the gate electrode.

公开(公告)号：JPH07307382A

公开(公告)日：1995-11-21

申请号：JP12457694

申请日：1994-05-13

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA

IPC: H01L21/76

Abstract: PURPOSE:To provide a trench element isolation structure which is never reduced its element isolation property in a subsequent heat treating process, and a method of forming the structure. CONSTITUTION:In a trench element isolation structure, which is formed by burying an insulating layer in a groove 12 formed in a semiconductor substrate 11, the insulating layer is formed in such a way that it consists of a silicon oxynitride layer 13 having a thermal expansion coefficient, which can be made roughly equal with that of the substrate 1. By this, a stress is hardly generated in the interface between the substrate 11 and the layer 13 by a subsequent heat-treating process and the generation of a crystal defect in the interface is decreased.

公开(公告)号：JPH07106414A

公开(公告)日：1995-04-21

申请号：JP26976393

申请日：1993-09-30

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA

IPC: H01L21/302 ,  H01L21/3065 ,  H01L21/76

Abstract: PURPOSE:To enhance reliability of a semiconductor device having trenches in the semiconductor substrate by providing a method for making a trench having no crystal defect in the inner wall and the surface layer. CONSTITUTION:In the first step, a trench 15 is made in a semiconductor substrate 11 by dry etching. In the second step, an antioxidizing material layer 16 is formed on the inner wall of the trench 15 such that the thickness t2 at the peripheral corner on the bottom face of the trench 15 will be thinner than the thickness t2 on the inner wall face thereof. In the third step, the semiconductor substrate 11 is heated in an oxidizing atmosphere to form a sacrificial oxide film 17 on the surface thereof. In the fourth step, the antioxidizing material layer 16 and the sacrificial oxide film 17 are removed by etching. This method allows removal by etching of the surface layer from the peripheral corner part on the bottom face of the trench 11 especially susceptible to crystal defect.

公开(公告)号：JPH06310459A

公开(公告)日：1994-11-04

申请号：JP12331093

申请日：1993-04-27

Applicant: SONY CORP

Inventor： KATAOKA TOYOTAKA

IPC: H01L21/28 ,  H01L21/302 ,  H01L21/3065 ,  H01L21/324 ,  H01L29/78 ,  H01L29/784

Abstract: PURPOSE:To prevent defects such as breakdown in case of etching electrode material on a substrate by dry etching. CONSTITUTION:Electrode material is formed on a substrate (I), oxidation is performed at need after patterning the material by dry etching (II) and heat treatment is performed in a gas atmosphere which contains nitrogen compound such as N2O and NH3 or halogen compound such as HCl, Cl2 and trichloroethane (III).

公开(公告)号：JP2010258472A

公开(公告)日：2010-11-11

申请号：JP2010156552

申请日：2010-07-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： O SHUNRI ,  HIRANO TOMOYUKI ,  KATAOKA TOYOTAKA ,  HAGIMOTO MASAYA

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/283 ,  H01L21/3205 ,  H01L21/768 ,  H01L21/8238 ,  H01L23/52 ,  H01L23/522 ,  H01L27/088 ,  H01L27/092 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To reduce resistance of a gate electrode of a high-breakdown-voltage transistor group by forming a low voltage operating transistor group and a high-breakdown-voltage (high-voltage-operation) transistor group on the same semiconductor substrate. SOLUTION: The semiconductor substrate 11 includes a first transistor group and a second transistor group of operating voltage lower than that of the first transistor group, wherein: the first transistor group includes a first gate electrode 15 formed on the semiconductor substrate 11 through a first gate insulating film 13, and a silicide layer 40 formed on the first gate electrode 15; the second transistor group includes second gate electrodes 47 and 48 formed in a gate formation groove 42 formed in an insulating film (a liner film 36 and a first interlayer dielectric 38) on the semiconductor substrate 11 through a second gate insulating film 43; and a protective film 41 covering the silicide layer 40 on the first gate electrode 15 of the first transistor group is formed. COPYRIGHT: (C)2011,JPO&INPIT

Abstract translation: 要解决的问题：为了通过在其上形成低电压工作晶体管组和高击穿电压（高电压操作）晶体管组来降低高击穿电压晶体管组的栅电极的电阻 相同的半导体衬底。 解决方案：半导体衬底11包括工作电压低于第一晶体管组的工作电压的第一晶体管组和第二晶体管组，其中：第一晶体管组包括形成在半导体衬底11上的第一栅电极15， 第一栅极绝缘膜13和形成在第一栅电极15上的硅化物层40; 第二晶体管组包括通过第二栅极绝缘膜43形成在形成在半导体衬底11上的绝缘膜（衬底膜36和第一层间电介质38）中的栅极形成沟槽42中的第二栅电极47和48; 并且形成覆盖第一晶体管组的第一栅电极15上的硅化物层40的保护膜41。 版权所有（C）2011，JPO＆INPIT

公开(公告)号：JP2009016706A

公开(公告)日：2009-01-22

申请号：JP2007179387

申请日：2007-07-09

Applicant: Sony Corp ,  ソニー株式会社

Inventor： O SHUNRI ,  HIRANO TOMOYUKI ,  KATAOKA TOYOTAKA ,  HAGIMOTO MASAYA

IPC: H01L21/8234 ,  H01L21/28 ,  H01L21/768 ,  H01L23/522 ,  H01L27/088 ,  H01L29/423 ,  H01L29/49

CPC classification number: H01L21/82385 ,  H01L21/823425 ,  H01L21/823468 ,  H01L21/823475 ,  H01L21/823835 ,  H01L21/823857 ,  H01L21/823871 ,  H01L2924/0002 ,  H01L2924/00

Abstract: PROBLEM TO BE SOLVED: To make resistance of a gate electrode of a high breakdown voltage transistor group low by forming a low voltage operating transistor group and a high breakdown voltage (high voltage operating) transistor group on one and the same semiconductor substrate. SOLUTION: The semiconductor substrate 11 includes a first transistor group and a second transistor group of operating voltage lower than the operating voltage of the first transistor group, wherein the first transistor group has a first electrode 15 formed on the semiconductor substrate 11 through a first gate insulating film 13, and a silicide layer 40 formed on the first gate electrode 15, the second transistor group has second gate electrodes 47 and 48 formed in a gate formation groove 42 formed in an insulating film (a liner film 36 and a first interlayer insulating film 38) on the semiconductor substrate 11 through a second gate insulating film 43, wherein a protective film 41 covering the silicide layer 40 on the first gate electrode 15 of the first transistor group is formed. COPYRIGHT: (C)2009,JPO&INPIT

Abstract translation: 要解决的问题：通过在同一半导体衬底上形成低电压工作晶体管组和高击穿电压（高电压工作）晶体管组来使高击穿电压晶体管组的栅电极的电阻变低 。 解决方案：半导体衬底11包括工作电压低于第一晶体管组的工作电压的第一晶体管组和第二晶体管组，其中第一晶体管组具有形成在半导体衬底11上的第一电极15，通过 第一栅极绝缘膜13和形成在第一栅电极15上的硅化物层40，第二晶体管组具有形成在形成于绝缘膜中的栅极形成槽42中的第二栅电极47和48（衬里膜36和 第一层间绝缘膜38），通过第二栅极绝缘膜43在半导体衬底11上形成覆盖第一晶体管组的第一栅电极15上的硅化物层40的保护膜41。 版权所有（C）2009，JPO＆INPIT