Programming memory cell of differential structure type employing CMOS technology and oxide layer capacitors

    公开(公告)号:FR2787911A1

    公开(公告)日:2000-06-30

    申请号:FR9816583

    申请日:1998-12-23

    Abstract: The integrated circuit for programmable memory employing Complementary Metal-Oxide-Semiconductor (CMOS) technology comprises at least two oxide layer capacitors (C0,C1) constituting a memory element for differential reading operation, and a circuit (1) for reading and programming operations containing transistors (P2,P3,P4,P5) of p-type conductivity in the first stage (2), where a relatively low voltage (Vdd) is used in the reading cycle, and a relatively high voltage (HV) in the programming or writing cycle. One of the capacitors, namely the capacitor (C0), is connected via a reading transistor (N0), asymmetric and of n-type conductivity, to the output stage (4), where the transistors is in the conducting state in the reading cycle. The circuit (1) contains at least two programming transistors (N2,N3) in the second stage (3), asymmetric and of n-type conductivity, with drains connected to the first terminals (10,11) of the capacitors (C0,C1). Each of the programming transistors (N2,N3) is connected in series with at least two transistors (P2,P3;P4,P5) forming at least two parallel branches between the high voltage (HV) terminal (12) and the ground (7), where the source of each of the two transistors (P2,P4) is connected to the voltage terminal (12). The second transistors (P3,P5) are connected between the first transistors (P2,P4) and the programming transistors (N2,N3), and the gates of transistors (P3,P5) are connected to an intermediate voltage (HV/2) terminal (13). In the second embodiment the circuit comprises two additional secondary parallel branches, each containing at least two transistors of p-type conductivity and a programming transistor, asymmetric and of n-type conductivity, where each primary branch contains at least three transistors of p-type conductivity. The programming transistors (N2,N3) are blocked in the reading cycle, and they are controlled by complementary signals (Vin, NVin) in the programming cycle.

Patent Agency Ranking